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ProASIC3E DC and Switching Characteristics
2-6
Revision 13
Calculating Power Dissipation
Quiescent Supply Current
Power per I/O Pin
Table 2-7 Quiescent Supply Current Characteristics
A3PE600
A3PE1500
A3PE3000
Typical (25掳C)
5 mA
12 mA
25 mA
Maximum (Commercial)
30 mA
70 mA
150 mA
Maximum (Industrial)
45 mA
105 mA
225 mA
Notes:
1. IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution, which is shown in
2. 鈥揊 speed grade devices may experience higher standby IDD of up to five times the standard IDD and higher I/O
leakage.
Table 2-8 Summary of I/O Input Buffer Power (per pin) 鈥� Default I/O Software Settings
VMV
(V)
Static Power
PDC2 (mW)1
Dynamic Power
PAC9 (W/MHz)2
Single-Ended
3.3 V LVTTL/LVCMOS
3.3
鈥�
17.39
3.3 V LVTTL/LVCMOS 鈥� Schmitt trigger
3.3
鈥�
25.51
3.3 V LVTTL/LVCMOS Wide Range3
3.3
鈥�
16.34
3.3 V LVTTL/LVCMOS Wide Range 鈥� Schmitt trigger3
3.3
鈥�
24.49
2.5 V LVCMOS
2.5
鈥�
5.76
2.5 V LVCMOS 鈥� Schmitt trigger
2.5
鈥�
7.16
1.8 V LVCMOS
1.8
鈥�
2.72
1.8 V LVCMOS 鈥� Schmitt trigger
1.8
鈥�
2.80
1.5 V LVCMOS (JESD8-11)
1.5
鈥�
2.08
1.5 V LVCMOS (JESD8-11) 鈥� Schmitt trigger
1.5
鈥�
2.00
3.3 V PCI
3.3
鈥�
18.82
3.3 V PCI 鈥� Schmitt trigger
3.3
鈥�
20.12
3.3 V PCI-X
3.3
鈥�
18.82
3.3 V PCI-X 鈥� Schmitt trigger
3.3
鈥�
20.12
Voltage-Referenced
3.3 V GTL
3.3
2.90
8.23
2.5 V GTL
2.5
2.13
4.78
3.3 V GTL+
3.3
2.81
4.14
2.5 V GTL+
2.5
2.57
3.71
Notes:
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.
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EMC61DRSN-S273 CONN EDGECARD 122PS DIP .100 SLD
EMC61DRSD-S273 CONN EDGECARD 122PS DIP .100 SLD
ASM44DSEI-S243 CONN EDGECARD 88POS .156 EYELET
A3PE3000-1FG324I IC FPGA 1KB FLASH 3M 324-FBGA
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