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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� M1A3P600-PQ208
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 9/12闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1KB FLASH 600K 208-PQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 24
绯诲垪锛� ProASIC3
RAM 浣嶇附瑷�(j矛)锛� 110592
杓稿叆/杓稿嚭鏁�(sh霉)锛� 154
闁€鏁�(sh霉)锛� 600000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 208-BFQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 208-PQFP锛�28x28锛�
ARM CortexTM-M1
6P ro d u c t B r i e f
stack. You can access the APSR with the MSR and
MRS instructions.
Interrupt PSR (IPSR) 鈥� Contains the Interrupt
Service Routine (ISR) number of the current
exception activation.
Execution PSR (EPSR) 鈥� Contains the Thumb state
bit (T-bit). Unless the processor is in Debug state,
the EPSR is not directly accessible. All fields read as
zero using an MRS instruction and MSR instruction
writes are ignored.
On entering an exception, the processor saves the
combined information from the three status registers on
the stack.
Special Purpose Priority Mask Register
Use the special purpose Priority Mask Register for
priority boosting. You can access the special purpose
Priority
Mask
Register
using
the
MSR
and
MRS
instructions. You can also use the CPS instruction to set or
clear PRIMASK.
Special Purpose Control Register
The special purpose Control Register identifies the stack
pointers used.
Data Types
The processor supports the following data types:
32-bit words
16-bit halfwords
8-bit bytes
Note: Unless otherwise stated, the core can access all
regions of the memory map, including the code region,
with all data types. To support this, the system must
support sub-word writes without corrupting neighboring
bytes in that word.
Memory Formats
The processor views memory as a linear collection of
bytes numbered in ascending order from 0 (Figure 3).
Figure 3 Processor Memory Map
0xE00FFFFF
0xF00FF000
0xE000ED00
0xE000E000
0xE0003000
0xE0002000
0xE0001000
0xE0000000
0xE000F000
0xE003FFFF
0xE0040000
0xE0041000
0xE0042000
ROM Table
Reserved
BP
DW
Reserved
NVIC
Debug Control
Reserved
0x3FFFFFFF
0x20100000
511 MB
1 MB
511 MB
1 MB
External
DTCM
External
ITCM
0x00100000
0x1FFFFFFF
0x20000000
0x00000000
Reserved
Internal Private Peripheral Bus
1 GB
0.5 GB
Code
SRAM
Peripheral
External
External Device
0.5 GB
0xFFFFFFFF
0xE0100000
0x5FFFFFFF
0x40000000
0x3FFFFFFF
0x20000000
0x1FFFFFFF
0x00000000
0x60000000
0x9FFFFFFF
0xA0000000
0xDFFFFFFF
0x00000000
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
A3P600-PQ208 IC FPGA 1KB FLASH 600K 208-PQFP
RMA43DTAT CONN EDGECARD 86POS R/A .125 SLD
HSM36DRAI CONN EDGECARD 72POS R/A .156 SLD
HMM36DRAI CONN EDGECARD 72POS R/A .156 SLD
HCC60DRYI-S734 CONN EDGECARD 120PS DIP .100 SLD
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
M1A3P600-PQ208I 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 600K 208-PQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:ProASIC3 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
M1A3P600-PQG144 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs
M1A3P600-PQG144ES 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs
M1A3P600-PQG144I 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs
M1A3P600-PQG144PP 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs