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鍨嬭櫉锛� M1A3P600-2FG484I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 2/12闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1KB FLASH 600K 484-FBGA
妯欐簴鍖呰锛� 40
绯诲垪锛� ProASIC3
RAM 浣嶇附瑷堬細 110592
杓稿叆/杓稿嚭鏁�(sh霉)锛� 235
闁€鏁�(sh霉)锛� 600000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 484-BGA
渚涙噳鍟嗚ō(sh猫)鍌欏皝瑁濓細 484-FPBGA锛�23x23锛�
ARM CortexTM-M1
10
Prod uct Bri e f
Bus Functional Model (BFM)
Introduction
During the development of an FPGA-based SoC, there
are various stages of testing that can be undertaken. This
can involve some, or all, of the following approaches:
Hardware simulation using Verilog or VHDL
Software simulation using a host-based instruction
set simulator (ISS) of the SoC鈥檚 processor
Hardware and software co-verification using a
full-functional model of the processor in Verilog,
VHDL or SWIFT form, or using a tool such as
Seamless
BFM Usage Flow
The BFM acts as a pin-for-pin replacement of the
Cortex-M1 in the simulation of the SoC subsystem. It
initiates bus transactions on the native ARM Cortex-M1
bus, which are cycle-accurate with real bus cycles that
ARM Cortex-M1 would produce. It does not have the
ability, however, to implement real ARM Cortex-M1
instructions. The BFM may be used to run a basic test
suite of the SoC subsystem, using the skeleton system
testbench.
You can edit the SoC Verilog/VHDL to add new design
blocks. You can also fill out the system-level testbench to
include tasks that test any newly added functionality, or
add stubs to allow more complex system testing
involving the IP cores. The BFM input scripts can also be
manually enhanced to test out access to register
locations in newly added logic. In this way, you can
provide stimuli to the system from the inside (via the
ARM Cortex-M1 BFM), as well as from the outside (via
testbench tasks).
Timing Shell
There is a timing shell provided for each ARM Cortex-M1
variant wrapped around the BFM. Therefore, the BFM is
bus cycle accurate, and performs setup/hold checks to
model output propagation delays.
Debug
The ARM Debug Architecture uses a protocol converter
box to allow the debugger to talk directly to the core via
a JTAG port. In effect, the scan chains in the core that are
required for test are re-used for debugging. The core
uses the scan chains to insert instructions directly into
ARM Cortex-M1. The instructions are executed on the
core and depending on the type of instruction that has
been inserted, the core or the system state can be
examined, saved, or changed. The architecture has the
ability to execute instructions at a slow debug speed or
to execute instructions at system speed.
In debug mode, the user can perform the following
functions:
Core halt
Core stepping
Core register access
Read/Write to TCMs
Read/Write to AHB address space
Breakpoint
Watchpoints
The main debug components are the following:
Debug control registers 鈥� to access and control
debugging of the core
Breakpoint Unit (BPU) 鈥� to implement breakpoints
Data Watchpoint Unit (DW) 鈥� to implement
watchpoints and trigger resources
Debug memory interfaces 鈥� to access external
ITCM and DTCM
ROM table
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
ACB106DHRQ-S621 CONN EDGECARD EXTEND 212POS .050
ABB106DHRQ-S621 CONN EDGECARD EXTEND 212POS .050
A3P600-2FGG484I IC FPGA 1KB FLASH 600K 484-FBGA
A3P600-2FG484I IC FPGA 1KB FLASH 600K 484-FBGA
M1AFS600-PQ208 IC FPGA 4MB FLASH 600K 208-PQFP
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