ARM CortexTM-M1 Prod uct Br ief 7 " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� M1A3P400-2FG144I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 10/12闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1KB FLASH 400K 144-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 160
绯诲垪锛� ProASIC3
RAM 浣嶇附瑷�(j矛)锛� 55296
杓稿叆/杓稿嚭鏁�(sh霉)锛� 97
闁€鏁�(sh霉)锛� 400000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 144-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-FPBGA锛�13x13锛�
ARM CortexTM-M1
Prod uct Br ief
7
For example:
Bytes 0鈥�3 hold the first stored word
Bytes 4鈥�7 hold the second stored word
The processor accesses data and code words in little-
endian format. Little-endian is the default memory
format for ARM processors.
In little-endian format, the byte with the lowest address
in a word is the least significant byte of the word. The
byte with the highest address in a word is the most
significant. The byte at address 0 of the memory system
connects to data lines 7鈥�0.
Exceptions
The processor and the Nested Vectored Interrupt
Controller (NVIC) prioritize and handle all exceptions. All
exceptions are handled in Handler mode. Processor state
is automatically stored to the stack on an exception, and
automatically restored from the stack at the end of the
exception handler Interrupt Service Routine (ISR). The
following
features
enable
efficient,
low-latency
exception handling:
Automatic
state
saving
and
restoring.
The
processor pushes state registers on the stack
before entering the ISR, and pops them after
exiting the ISR with no instruction overhead.
Automatic reading of the vector table entry that
contains the ISR address in code memory or data
SRAM
Closely-coupled interface between the processor
and the NVIC to enable early processing of
interrupts
and
processing
of
late-arriving
interrupts with higher priority
Fixed number of interrupt priorities, from 2 bits, 4
levels
Separate stacks for Handler and Thread modes if
OS extensions are implemented
ISR control transfer using the calling conventions
of the C/C++ standard Procedure Call Standard for
the ARM Architecture (PCSAA)
Priority masking to support critical regions
Exception Types
Various types of exceptions exist in the processor. A fault
is an exception that results from an error condition.
Faults can be reported synchronously or asynchronously
to the instruction that caused them. In general, faults are
reported synchronously. Faults caused by writes over the
bus are asynchronous faults. A synchronous fault is
always reported with the instruction that caused the
fault. An asynchronous fault does not guarantee how it
is reported with respect to the instruction that caused
the fault. See Table 3 for a list and description of the
exceptions supported by ARM Cortex-M1
.
Table 3
Exception Types
Position
Exception
Type
Priority
Description
Activated
鈥�
Stack top is loaded from first entry of vector table on Reset.
鈥�
1
Reset
鈥�3 (highest)
Invoked on power-up and warm Reset. On first instruction,
drops to lowest priority. Thread mode.
Asynchronous
2
Non-maskable
鈥�2
Cannot be marked, prevented by activation, by any other
exception. Cannot be preempted by any other exception
other than Reset.
Asynchronous
3
Hard fault
鈥�1
All classes of fault
Synchronous or
asynchronous
4鈥�10
鈥�
Reserved
鈥�
11
SVCall
Configurable
System service call with SVC instruction
Synchronous
12鈥�13
鈥�
Reserved
鈥�
14
PendSV
Configurable
Pendable request for system service. This is only pended by
software.
Asynchronous
15
SysTick
Configurable
System tick timer has fired.
Asynchronous
16鈥�48
External
interrupt
Configurable
Asserted from outside the processor, IRQ[2n-1:0], and fed
through the NVIC (prioritized).
Asynchronous
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
IDT71024S12TYG IC SRAM 1MBIT 12NS 32SOJ
M1A3P400-2FGG144I IC FPGA 1KB FLASH 400K 144-FBGA
IDT71024S15TYG IC SRAM 1MBIT 15NS 32SOJ
A3P400-FG256I IC FPGA 1KB FLASH 400K 256-FBGA
IDT71024S12YG IC SRAM 1MBIT 12NS 32SOJ
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
M1A3P400-2FG144PP 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs
M1A3P400-2FG256 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 400K 256-FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
M1A3P400-2FG256I 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 400K 256-FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
M1A3P400-2FG484 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 400K 484-FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
M1A3P400-2FG484I 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 400K 484-FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�