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ARM CortexTM-M1
4P ro d u c t B r i e f
ARM Cortex-M1 Signals
The signals of the core are given in Table 2.
Table 2
ARM Cortex-M1 Signal Descriptions
Name
Width
Type
Description
HCLK
1
Input
Main processor clock
NSYSRESET
1
Input
External push-button/power-up reset
WDOGRES
1
Input
Watchdog reset to ARM Cortex-M1
WDOGRESn
1
Output
Reset of watchdog timer
HRESETn
1
Output
Reset to other components in AHB system
RV_TCK
1
Input
RealView JTAG
RV_nTRST
1
Input
RealView JTAG
RV_TMS
1
Input
RealView JTAG
RV_TDI
1
Input
RealView JTAG
RV_nSRST_IN
1
Input
RealView JTAG
RV_TRCK
1
Input
RealView JTAG
RV_TDOUT
1
Output
RealView JTAG
RV_nTDOEN
1
Output
RealView JTAG
UJTAG_TCK
1
Input
FlashPro3 JTAG
UJTAG_TDI
1
Input
FlashPro3 JTAG
UJTAG_TMS
1
Input
FlashPro3 JTAG
UJTAG_TRSTB
1
Input
FlashPro3 JTAG
UJTAG_TDO
1
Output
FlashPro3 JTAG
IRQ[31:0]
32
Input
External Interrupts
NMI
1
Input
Non-maskable Interrupt
EDBGRQ
1
Input
External debug request
nTRST
1
Input
JTAG reset
JTAGTOP
1
Output
State Controller Indicator
nTDOEN
1
Output
JTAG data out enable
LOCKUP
1
Output
Core is locked up
HALTED
1
Output
Core is in Halt Debug state
HREADY
1
Input
Slave ready signal
HRESP
1
Input
AHB response signal
HRDATA[31:0]
32
Input
Data from Slave to Master
HTRANS[1:0]
2
Output
AHB transfer type signal
HBURST[2:0]
3
Output
AHB burst signal
HPROT[3:0]
4
Output
Transfer protection bits
HSIZE[2:0]
3
Output
Transfer size
HWRITE
1
Output
Transfer direction
HMASTLOCK
1
Output
Transfer is part of a locked sequence
HADDR[31:0]
32
Output
Transfer address
HWDATA[31:0]
32
Output
Data from Master to Slave
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