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鍨嬭櫉(h脿o)锛� M1A3P1000-1FGG144
寤犲晢锛� Microsemi SoC
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鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA M1 1KB FLASH 1M 144FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 160
绯诲垪锛� ProASIC3
RAM 浣嶇附瑷�(j矛)锛� 147456
杓稿叆/杓稿嚭鏁�(sh霉)锛� 97
闁€(m茅n)鏁�(sh霉)锛� 1000000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 144-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-FPBGA锛�13x13锛�
ARM CortexTM-M1
10
Prod uct Bri e f
Bus Functional Model (BFM)
Introduction
During the development of an FPGA-based SoC, there
are various stages of testing that can be undertaken. This
can involve some, or all, of the following approaches:
Hardware simulation using Verilog or VHDL
Software simulation using a host-based instruction
set simulator (ISS) of the SoC鈥檚 processor
Hardware and software co-verification using a
full-functional model of the processor in Verilog,
VHDL or SWIFT form, or using a tool such as
Seamless
BFM Usage Flow
The BFM acts as a pin-for-pin replacement of the
Cortex-M1 in the simulation of the SoC subsystem. It
initiates bus transactions on the native ARM Cortex-M1
bus, which are cycle-accurate with real bus cycles that
ARM Cortex-M1 would produce. It does not have the
ability, however, to implement real ARM Cortex-M1
instructions. The BFM may be used to run a basic test
suite of the SoC subsystem, using the skeleton system
testbench.
You can edit the SoC Verilog/VHDL to add new design
blocks. You can also fill out the system-level testbench to
include tasks that test any newly added functionality, or
add stubs to allow more complex system testing
involving the IP cores. The BFM input scripts can also be
manually enhanced to test out access to register
locations in newly added logic. In this way, you can
provide stimuli to the system from the inside (via the
ARM Cortex-M1 BFM), as well as from the outside (via
testbench tasks).
Timing Shell
There is a timing shell provided for each ARM Cortex-M1
variant wrapped around the BFM. Therefore, the BFM is
bus cycle accurate, and performs setup/hold checks to
model output propagation delays.
Debug
The ARM Debug Architecture uses a protocol converter
box to allow the debugger to talk directly to the core via
a JTAG port. In effect, the scan chains in the core that are
required for test are re-used for debugging. The core
uses the scan chains to insert instructions directly into
ARM Cortex-M1. The instructions are executed on the
core and depending on the type of instruction that has
been inserted, the core or the system state can be
examined, saved, or changed. The architecture has the
ability to execute instructions at a slow debug speed or
to execute instructions at system speed.
In debug mode, the user can perform the following
functions:
Core halt
Core stepping
Core register access
Read/Write to TCMs
Read/Write to AHB address space
Breakpoint
Watchpoints
The main debug components are the following:
Debug control registers 鈥� to access and control
debugging of the core
Breakpoint Unit (BPU) 鈥� to implement breakpoints
Data Watchpoint Unit (DW) 鈥� to implement
watchpoints and trigger resources
Debug memory interfaces 鈥� to access external
ITCM and DTCM
ROM table
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
A3P1000-1FG144 IC FPGA 1KB FLASH 1M 144-FBGA
A40MX04-2PQ100I IC FPGA MX SGL CHIP 6K 100-PQFP
IDT71024S15YGI IC SRAM 1MBIT 15NS 32SOJ
IDT71V256SA12PZG IC SRAM 256KBIT 12NS 28TSOP
IDT71024S20YGI IC SRAM 1MBIT 20NS 32SOJ
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鍙冩暩(sh霉)鎻忚堪
M1A3P1000-1FGG144ES 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū(ch膿ng):Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs
M1A3P1000-1FGG144I 鍔熻兘鎻忚堪:IC FPGA M1 1KB FLASH 1M 144FPGA RoHS:鏄� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪锛� 绯诲垪:ProASIC3 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€(m茅n)鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤�(l猫i)鍨�:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�
M1A3P1000-1FGG144M 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA PROASIC?3 FAMILY 1M GATES 130NM (CMOS) TECHNOLOGY 1.5V - Trays 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:IC FPGA 97 I/O 144GBGA
M1A3P1000-1FGG144PP 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū(ch膿ng):Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs
M1A3P1000-1FGG256 鍔熻兘鎻忚堪:IC FPGA M1 1KB FLASH 1M 256FBGA RoHS:鏄� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪锛� 绯诲垪:ProASIC3 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€(m茅n)鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤�(l猫i)鍨�:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�