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M1025/26 Datasheet Rev 1.0
6
of 14
Revised 28Jul2004
Integrated Circuit Systems, Inc.
●
Networking & Communications
●
www.icst.com
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tel (508) 852-5400
Integrated
Circuit
Systems, Inc.
M1025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
P r o d u c t D a t a S h e e t
TriState
The TriState feature puts the LVPECL output driver into
a high impedance state, effectively disconnecting the
driver from the
FOUT
and
nFOUT
pins of the device. A
logic
0
is then present on the clock net. The impedance
of the clock net is then set to 50
by the external circuit
resistors. (This is in distinction to a CMOS output in
TriState, in which case the net goes to a high
impedance and the logic value floats.) The 50
impedance level of the LVPECL TriState allows
manufacturing In-circuit Test to drive the clock net with
an external 50
generator to validate the integrity of
clock net and the clock load.
Any unused output (single-ended or differential) should
be left unconnected (floating) in system application.
This minimizes output switching current and therefore
minimizes noise modulation of the VCSO.
Loss of Lock Indicator (
LOL
) Output Pin
Under normal device operation, when the PLL is locked,
the LOL Phase Detector drives
LOL
to logic
0
. Under
circumstances when the VCSO cannot lock to the input
(as measured by a greater than 4 ns discrepancy
between the feedback and reference clock rising edges
at the LOL Phase Detector) the
LOL
output goes to logic
1. The
LOL
pin will return back to logic
0
when the phase
detector error is less than 2 ns. The loss of lock
indicator is a low current LVCMOS output.
Guidelines Using LOL
As described, the
LOL
pin indicates when the PLL is
out-of-lock with the input reference. The LOL condition
is also used by the AutoSwitch circuit to detect a lost
reference, as described in following sections. LOL is
also used by the Hitless Switching and Phase Build-out
functions (optional device features).
To ensure reliable operation of LOL and guard against
false out-of-lock indications, the following conditions
should be met:
The phase detector frequency should be no less than
5MHz
, and preferably it should be
10MHz
or greater.
Phase detector frequency is defined by Fin / R.
A higher phase detector frequency will result in lower
phase error and less chance of false triggering the
LOL phase detector. Refer to Tables
3
and
4 on pg. 3
for phase detector frequency when using the
M1025-11-155.5200
or the
M1026-11-155.5200
.
The input reference should have an intrinsic jitter of
less than 1 ns pk-pk. If reference jitter is greater than
1 ns pk-pk, the LOL circuit might falsely trigger. Due
to this limitation, the LOL circuit should not be used in
loop timing mode, nor should it be used with a noisy
reference clock. Likewise, the AutoSwitch, Hitless
Switching, or Phase Build-out features should not be
used in loop timing mode or with a noisy reference
clock, since these features depend on LOL
.
Reference Acknowledgement (
REF_ACK
) Output
The
REF_ACK
(reference acknowledgement) pin outputs
the value of the reference clock input that is routed to
the phase detector. Logic
1
indicates input pair
1
(
nDIF_REF1, DIF_REF1
);
l
ogic
0
indicates input pair
0
(
nDIF_REF0, DIF_REF0
)
.
The
REF_ACK
indicator is an
LVCMOS output.