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參數(shù)資料
| 型號： | M100LVEP111FATWG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:10 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | 100LVEP |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | ECL，HSTL，PECL |
| 輸出： | ECL，PECL |
| 頻率 - 最大： | 3GHz |
| 電源電壓： | 2.375 V ~ 3.8 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
MC100LVEP111
http://onsemi.com
7
Table 9. AC CHARACTERISTICS V= 0 V; VEE = 2.375 to 3.8 V or VCC = 2.375 to 3.8 V; VEE = 0 V (Note 14)
Symbol
40°C
25°C
85°C
Unit
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
3
GHz
tPLH
tPHL
Propagation Delay
(Differential Configuration)
325
400
475
350
430
500
375
510
590
ps
tskew
WithinDevice Skew (Note 15)
WithinDevice Skew @ 2.5 V (Note 15)
DevicetoDevice Skew (Note 16)
20
85
25
150
20
85
25
150
25
20
85
35
25
150
ps
tJITTER
CLOCK Random Jitter (RMS)
@ v0.5 GHz
@ v1.0 GHz
@ v1.5 GHz
@ v2.0 GHz
@ v2.5 GHz
@ v3.0 GHz
0.209
0.200
0.197
0.220
0.232
0.348
0.5
0.4
0.5
0.4
0.6
0.204
0.214
0.213
0.224
0.290
0.545
0.5
0.6
0.5
0.8
0.221
0.229
0.243
0.292
0.522
0.911
0.5
0.4
0.6
0.8
1.3
ps
tjit(f)
Additive RMS Integrated Phase Jitter
(fc = 156.25 MHz, 12 kHz 20 MHz)
149
fs
VPP
Input Swing (Differential Interconnect
Configuration) Measured SingleEnded
150
800
1200
150
800
1200
150
800
1200
mV
tr/tf
Output Rise/Fall Time (20%80%)
105
200
255
125
200
275
150
230
320
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
14.Measured with 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC 2.0 V.
15.Skew is measured between outputs under identical transitions and conditions on any one device.
16.DevicetoDevice skew for identical transitions at identical VCC levels.
0
100
200
300
400
500
600
700
800
0
1000
2000
3000
4000
5000
6000
Figure 4. Fmax Typical
FREQUENCY (MHz)
V
OUTpp
(mV)
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