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參數(shù)資料
| 型號： | LZ34B1B |
| 英文描述： | CMOS IMAGE SENSORS |
| 中文描述： | CMOS圖像傳感器 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 144K |
| 代理商： | LZ34B1B |
PRELMNARY
SCLK
LZ34B1B
8
[Monitoring Mode]
CLK
ADOUT
(D
0
-D
7
)
Normal
HD
CLK
ADOUT
(D
0
-D
7
)
776
4
OB
OB
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
80
84
88
92
HORIZONTAL PULSE TIMING
PHASE RELATIONS BETWEEN DIGITAL OUTPUT (ADOUT) AND CLOCK (CLK)
VERTICAL PULSE TIMING
ππππππππππππππ
OB
OB
ππππππππππππππ
Mirror
10
5
1
CLK
ADOUT
(D
0
-D
7
)
Normal
HD
74
78
82
86
90
94
98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170
Mirror
ADOUT
(D
0
-D
7
)
Mirror
780
012
HD
SDI
AGC
VD
261262
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
SDI, SCLK, LOAD Forbidden Period
37 38
41
38
37
34
33
30
29
26
25
22
21
18
17
14
13
10
9
6
5
2
1
OB
42
260
489490493
OB
486
D
0
D
10
D
20
D
30
D
37
SYMBOL
MIN.
TYP.
MAX.
UNIT
t
45
ns
453
456
457
460
461
464
465
468
469
472
473
476
477
480
481
484
485
488
489
492
493
OB
452
5
4
1
OB
8
LOAD
SERIAL DATA TIMING (SDI, SCLK, LOAD)
Fixed
Gain
Shutter
Offset
t
The rising edge of the HD pulse must be between two rising edges of CLK (0) and CLK (1).
The falling edge of the HD pulse must be between two rising edges of CLK (78) and CLK (79).
The rising edge and falling edge of the VD pulse must be in high period of the HD pulses.
Data in SDI are taken at the rising edge of SCLK.
Clock frequency of SCLK should be less than 1/2 of that of CLK.
Do not insert the SDI, SCLK and LOAD pulses between 15H
*
and 16H
*
. Refer to "
VERTICAL PULSE TIMING
".
Refer to
"SERIAL DATA INPUTS"
for the contents of serial data from D
0
to D
37
.
* It means ordinal number of the HD pulse.
645
650
655
ππππππππππππππ
ππππππππππππππ
OB
1
OB
5
10
15
20
25
30
35
40
OB
655
OB
650
645
640
635
630
625
620
615
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