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參數資料
| 型號： | LXT360PE |
| 英文描述： | PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|LDCC|28PIN|PLASTIC |
| 中文描述： | 的PCM收發(fā)器|單|優(yōu)稅PCM-30/E-1 |的CMOS | LDCC | 28腳|塑料 |
| 文件頁數： | 29/52頁 |
| 文件大?。?/td> | 1187K |
| 代理商： | LXT360PE |
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Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
—
LXT361
Datasheet
29
Table 11. Interrupt Clear Register
Read/Write, Address (A7-A0) = x010011x
Bit
Name
Function
1
0
CLOS
1 = Clear/Mask Loss of Signal interrupt.
0 = Enable Loss of Signal interrupt.
1
CNLOOP
1 = Clear/Mask Network loopback interrupt.
0 = Enable Network loopback interrupt.
2
CAIS
1 = Clear/Mask Alarm Indication Signal interrupt.
0 = Enable Alarm Indication Signal interrupt.
3
CQRSS
1 = Clear/Mask Quasi-Random Signal Source interrupt.
0 = Enable Quasi-Random Signal Source interrupt.
4
-
reserved
–
set to 1 for normal operation.
5
CDFMO
1 = Clear/Mask Driver Failure Monitor Open interrupt.
0 = Enable Driver Failure Monitor Open interrupt.
6
CESO
1 = Clear/Mask Elastic Store Overflow interrupt.
0 = Enable Elastic Store Overflow interrupt.
7
CESU
1 = Clear/Mask Elastic Store Underflow interrupt.
0 = Enable Elastic Store Underflow interrupt.
1. Leaving a 1 of in any of these bits masks the associated interrupt.
Table 12. Transition Status Register
Read Only, Address (A7-A0) = x010100x
Bit
Name
Function
0
TLOS
1 = Loss of Signal (LOS) has changed since last clear LOS interrupt occurred.
0 = No change in status.
1
TNLOOP
1 = NLOOP has changed since last clear NLOOP interrupt occurred.
0 = No change in status.
2
TAIS
1 = AIS has changed since last clear AIS interrupt occurred.
0 = No change in status.
3
TQRSS
1 = QRSS has changed since last clear QRSS interrupt occurred
1
.
0 = No change in status.
4
-
reserved-ignore.
5
TDFMO
1 = DFMO has changed since last clear DFMS interrupt occurred.
0 = No change in status.
6
ESOVR
1 = ES overflow status sticky bit
2
.
0 = No change in status.
7
ESUNF
1 = ES underflow status sticky bit
2
.
0 = No change in status.
1. A QRSS transition indicates receive QRSS pattern sync or loss. A simple error in QRSS pattern is not reported as a
transition.
2. Tripping the overflow or underflow indicator in the ES sets the ESOVR/ESUNF status bit(s). Reading the Transition Status
Register clears these bits. Setting CESO and CESU in the Interrupt Clear Register masks these interrupts.
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PDF描述 |
|---|---|
| LXT384BE | Telecomm/Datacomm |
| LXT384LE | Telecomm/Datacomm |
| LXT386BE | PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|BGA|160PIN|PLASTIC |
| LXT386LE | PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| LXT388LE | PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| LXT360QE | 制造商:Intel 功能描述: 制造商:LEVEL ONE 功能描述: |
| LXT361 | 制造商:LVL1 制造商全稱:LVL1 功能描述:Integrated T1/E1 LH/SH Transceivers for DS1/DSX-1/CSU or NTU/ISDN PRI Applications |
| LXT361LE | 制造商:LEVEL ONE 功能描述:361LE |
| LXT361PE | 制造商:LEVEL 1 功能描述: 制造商:LEVEL ONE 功能描述: 制造商:Intel 功能描述:PCM TRANSCEIVER, Single, CEPT PCM-30/E-1, 28 Pin, Plastic, PLCC |
| LXT361QE | 制造商:LEVEL ONE 功能描述: 制造商:LEVEL ONE 功能描述:DATACOM, PCM TRANSCEIVER, PQFP44 |
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