參數(shù)資料
型號(hào)： LXT318NE
英文描述： PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|DIP|28PIN|PLASTIC
中文描述： 的PCM收發(fā)器|單|優(yōu)稅PCM-30/E-1 |的CMOS |雙酯| 28腳|塑料
文件頁(yè)數(shù)： 13/26頁(yè)
文件大?。?/td> 402K
代理商： LXT318NE
T1 CSU/ISDN PRI Transceiver
—
LXT310
Datasheet
13
.
2.5.2
Hardware Mode Operation
In Hardware mode the transceiver is accessed and controlled through individual pins. With the
exception of the INT and CLKE functions, Hardware mode provides all the functions provided in
the Host mode. In the Hardware mode RPOS/RNEG or RDATA outputs are valid on the rising
edge of RCLK. The LXT310 operates in Hardware mode only when MODE is set Low or
connected to RCLK.
Figure 5. LXT310 Serial Interface Data Structure
Table 3. LXT310 Serial Data Output Bits
(See
Figure 5
)
Bit
D5
Bit
D6
Bit
D7
Status
0
0
0
Reset has occurred, or no program input.
0
0
1
TAOS is active.
0
1
0
Local Loopback is active.
0
1
1
TAOS and Local Loopback are active.
1
0
0
Remote Loopback is active.
1
0
1
DPM has changed state since last Clear
DPM occurred.
1
1
0
LOS has changed state since last Clear
LOS occurred.
1
1
1
LOS and DPM have both changed state
since last Clear DPM and Clear LOS
occurred.
CS
SCLK
SDI/ SDO
ADDRESS /
COMMAND
BYTE
INPUT
DATA
BYTE
R/W
A0
A1
A2
A3
A4
A5
D0
D1
D2
D3
D4
D5
D6
D7
A6
ADDRESS / COMMAND BYTE
DATA INPUT / OUTPUT BYTE
LOS
D0 (LSB)
NLOOP
B8ZS
LBO1
LBO2
RLOOP
LLOOP
TAOS
D7(MSB)
1=ENABLE
R/W
0
A0
0
0
0
0
1
A4
X
A6
CLEAR INTERRUPTS
SET DIAGNOSTICS OR RESET
X=DON
’
T CARE
R/W- = 1: Read
R/W- = 0: Write
NOTE:
Output data byte is
the same as the input
data byte except for
bits D<5:7> shown in
Table 3
.
1=ENABLE
1=ENABLE
1=ENABLE
1=ENABLE
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