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參數(shù)資料
| 型號： | LXT312NE |
| 英文描述： | PCM REPEATER|T-1(DS1)|CMOS|DIP|16PIN|PLASTIC |
| 中文描述： | 的PCM直放站|的T 1（DS1的）|的CMOS |雙酯| 16PIN |塑料 |
| 文件頁數(shù)： | 22/26頁 |
| 文件大小： | 402K |
| 代理商： | LXT312NE |
LXT310
—
T1 CSU/ISDN PRI Transceiver
22
Datasheet
425
120
500
95
500
105
600
90
675
105
650
50
725
5
650
-45
1100
5
800
-45
1250
5
896
-26
1100
-5
1250
-5
Table 12. LXT310 Receive Timing Characteristics
(See
Figure 10
)
Parameter
Sym
Min
Typ
1
Max
Units
Receive clock duty cycle
2
RCLKd
40
50
60
%
Receive clock period
t
PW
600
648
700
ns
Receive clock pulse width high
t
PWH
–
324
–
ns
Receive clock pulse width low
t
PWL
303
324
345
ns
RPOS/RNEG to RCLK rising setup time
t
SUR
–
274
–
ns
RCLK rising to RPOS/RNEG hold time
t
HR
–
274
–
ns
1. Typical values are at 25
°
C and are for design aid only; they are not guaranteed and not subject to production testing.
2. RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Max and Min RCLK duty cycles
are for worst case jitter conditions (0.4 UI clock displacement for 1.544 MHz).
Figure 10. LXT310 Receive Clock Timing Diagram
Table 11. Pulse Mask Corner Point Specifications
Maximum Curve
Minimum Curve
Time (ns)
% V
Time (ns)
% V
t
PWL
t
PWH
t
PW
t
HR
t
SUR
RCLK
RPOS
RNEG
RPOS
RNEG
t
SUR
t
HR
Host mode
CLKE = 1
Host mode
CLKE = 0, &
H/W mode
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