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參數資料
| 型號： | LX64EV-5FN100I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數： | 7/9頁 |
| 文件大小： | 0K |
| 描述： | IC SWITCH DIGITAL 100FPBGA |
| 產品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標準包裝： | 176 |
| 功能： | 開關 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LBGA |
| 供應商設備封裝： | 100-FPBGA（11x11） |
| 包裝： | 托盤 |
Lattice Semiconductor
ispGDX2 Family Data Sheet
4
MUX and Register Block (MRB)
Every MRB Block has a 4:1 MUX (I/O MUX) and a set of three registers which are connected to the I/O buffers,
FIFO and sysHSI Blocks. Multiple MRBs can be combined to form large multiplexers as described below. Figure 3
shows the structure of the MRB.
Each of the three registers in the MRB can be congured as edge-triggered D-type ip-op or as a level sensitive
latch. One register operates on the input data, the other output data and the last register synchronizes the output
enable function. The input and output data signals can bypass each of their registers. The polarity of the data out
and output enable signals can be selected.
The Output and OE register share the same clock and clock enable signals. The Input register has a separate clock
and clock enable. The initialization signals of each register can be independently congured as Set or Reset. These
registers have programmable polarity control for Clock, Clock Enable and Set/Reset. The output enable register
input can be set either by one of the two output enables generated locally from the Control Array or from one of the
four (two in 64 I/O) Global OE enable pins. In addition to the local clock and clock enable signals, each MRB has
access to Global Clock, Clock Enable, Reset and TOE nets.
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