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參數(shù)資料
| 型號(hào)： | LX1742 |
| 廠(chǎng)商： | Microsemi Corporation |
| 英文描述： | High Efficiency High Voltage Boost Controller |
| 中文描述： | 高效率高電壓升壓控制器 |
| 文件頁(yè)數(shù)： | 7/13頁(yè) |
| 文件大?。?/td> | 456K |
| 代理商： | LX1742 |
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Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 7
Copyright
2000
Rev. 1.0b, 2005-03-03
W
M
.
C
LX1742
High Efficiency High Voltage Boost Controller
P
RODUCTION
D
ATA
S
HEET
I N T E G R A T E D P R O D U C T S
A P P L I C A T I O N I N F O R M A T I O N ( C O N T I N U E D )
O
UTPUT
R
IPPLE
C
APACITOR
S
ELECTION
Output voltage ripple is a function of the inductor value
(L), the output capacitor value (C
OUT
), the peak switch
current setting (I
PEAK
), the load current (I
OUT
), the input
voltage (V
IN
) and the output voltage (V
OUT
) for a this
boost converter regulation scheme. When the switch is
first turned on, the peak-to-peak voltage ripple is a
function of the output droop (as the inductor current
charges to I
PEAK
), the feedback transition error (i.e.,
typically 10mV), and the output overshoot (when the
stored energy in the inductor is delivered to the load at the
end of the charging cycle). Therefore the total ripple
voltage is
V
RIPPLE
=
V
DROOP
+
V
OVERSHOOT
+ 10mV
The initial droop can be estimated as follows where the
1.2 value in the denominator is an estimate of the typical
voltage drop across the inductor and the internal FET’s
R
DS_ON
:
L
=
(
)
(
)
1.2
V
I
I
C
V
IN
OUT
PK
OUT
DROOP
×
×
The output overshoot can be estimated as follows
where the 0.5 value in the denominator is an estimate of
the voltage drop across the diode:
(
)
(
)
IN
OUT
V
2
OUT
PK
OUT
2
1
OVERSHOOT
V
V
0.5
I
I
C
L
+
×
×
=
D
ESIGN
E
XAMPLE
:
Determine the V
RIPPLE
where I
PK
equals 200mA, I
OUT
equals 35mA, L equals 47
μ
H, C
OUT
equals 4.7
μ
F, V
IN
equals 3.0V, and V
OUT
equals 18.0V:
(
)
(
)
mV
8
3
1.2
3.0
35mA
200mA
F
4.7
H
47
V
DROOP
=
×
×
=
μ
μ
(
)
(
)
mV
4
0
0.5
0
1
mA
5
3
mA
200
F
4.7
H
μ
47
V
2
2
1
OVERSHOOT
=
+
×
μ
×
=
Therefore, for C
OUT
equals 4.7
μ
F:
V
RIPPLE
= 38mV + 9.4mV + 10mV = 57.4mV
Increasing the output capacitor value results in the
reduction of the output voltage ripple voltage. Low ESR
capacitors are recommended to reduce ripple caused by the
switching current. Multi-layer ceramic capacitors with
X5R or X7R dielectric are a superior choice featuring small
size, very low ESR, and a temperature stable dielectric.
Low ESR electrolytic capacitors such as solid tantalum or
OS-CON types are also acceptable. Moreover, adding a
capacitor from the output to the feedback pin (C2) allows
the internal feedback circuitry to respond faster which
further minimizes output voltage ripple and reduces noise
coupling into the high impedance feedback input.
D
IODE
S
ELECTION
A Schottky diode is recommended for most applications
(e.g. Microsemi
UPS5819
). The low forward voltage drop
and fast recovery time associated with this type of device
supports the switching demands associated with this circuit
topology. The designer is encouraged to consider the
diode’s average and peak current ratings with respect to the
application’s output and peak inductor current requirements.
Further,
the
diode’s
reverse
characteristic must be capable of withstanding a
negative
voltage transition that is greater than V
OUT
.
The LX1742 has a built in diode that may be used instead of an
external device. Using this internal diode reduces system cost
however, overall efficiency decreases. The electrical connections
corresponding to use of the internal diode are shown in Figure 3.
In this configuration, the inductor is connected between the input
source and the SW pin (1). The output is taken directly from OUT
pin (8).
breakdown
voltage
PCB
L
AYOUT
The LX1742 produces high slew-rate voltage and current
waveforms hence; the designer should take this into
consideration when laying out the circuit. Minimizing trace
lengths from the IC to the inductor, diode, input and output
capacitors, and feedback connection (i.e., pin 3) are typical
considerations. Moreover, the designer should maximize
the DC input and output trace widths to accommodate peak
current levels associated with this circuit.
A
P
P
L
I
C
A
T
I
O
N
S
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