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參數(shù)資料
| 型號(hào)： | LX1705ILQ-TR |
| 廠商： | MICROSEMI CORP-ANALOG MIXED SIGNAL GROUP |
| 元件分類(lèi)： | 音頻／視頻放大 |
| 英文描述： | 8 W, 2 CHANNEL, AUDIO AMPLIFIER, PQCC32 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, MLPQ-32 |
| 文件頁(yè)數(shù)： | 11/17頁(yè) |
| 文件大?。?/td> | 378K |
| 代理商： | LX1705ILQ-TR |
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LX1705
PRODUCTION DATA SHEET
Microsemi
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 3
Copyright
2007
Rev. 1.2, 2007-03-20
WWW
.Microse
m
i
.CO
M
8+8W Stereo Filterless Class-D Amplifier
TM
FUNCTIONAL PIN DESCRIPTION
Name
Function
Pin
Number(s)
Description
PVSS1P
PVSS1N
PVSS2P
PVSS2N
Power
Ground
32
25
16
9
Power Ground for the two H-bridge output drivers, connect to power ground plane
PVDD1
PVDD2
Power
Supply
28,29
12,13
Power Supply for the two H-bridge output drivers. Current draw will be up to 1.6A at 2
x 8W into 8. These are peak currents when the part is run at maximum rated power
on both channels.
V5V
Power
Supply
18
Analog Power Supply for the analog signal processing section.
AVSS1
AVSS2
Analog
Ground
19
22
Analog Ground for the analog signal processing section. Must be at the same potential
as PVSS, connect at one point to the power ground plane.
IN1N
IN1P
IN2N
IN2P
Analog
Input
3
2
6
7
Differential analog audio inputs for each channel. The common mode voltage will be
set by the LX1705 to around 2.25V.
OUT1N
OUT1P
OUT2N
OUT2P
Digital
Output
26
31
15
10
Differential high power audio outputs for each channel. Each output will swing
between PVDD and PVSS. These outputs are driven by an on-chip H-bridge output
driver which uses low RDSON NFETs.
BOOT1N
BOOT1P
BOOT2N
BOOT2P
Bootstrap
27
30
14
11
Bootstrap voltage pins which provide the high voltage needed to drive the upper NFET.
A bootstrap capacitor should be placed between the respective output and these pins.
VREF
Analog
Output
20
Typical 2.25V reference voltage which serves as an internal reference. An external
compensation capacitor of at least 1uF should be connected between this pin and
AVSS.
MUTE
CMOS
Input
8
Logic level control which mutes the audio signal when high.
STBY
CMOS
Input
1
Logic level control which places the chip into sleep mode when high.
STATUS
CMOS
Output
17
Digital monitoring pin which is used to flag internal fault states. This pin will be
synchronized with the internal clock to prevent glitches. See the STATUS flag list
(below) for a summary of which conditions will force this pin to go high.
ROSC
Analog
Input
21
Frequency control pin. A resistor between this pin and AVSS will set the oscillation
frequency for the Class-D modulator.
TCTRL
Test Pin
24
Test purpose only, Connect to AVSS1
TMON
Test Pin
23
Test purpose only, left open.
N.C.
No
connect
4,5
No Connect, pin is open
The STATUS pin will go high under any of the following conditions:
STBY is high. This indicates that the chip is in “stand-by” mode.
V5V is below the V5V UVLO threshold.
PVDD is below the PVDD UVLO threshold.
The die temperature is above about 140°C. This indicates that the part has gone in to gain foldback.
A short circuit across the speaker has caused the output devices to shut off due to excessive temperature.
PP
AA
CC
KK
AA
GG
EE
DD
AA
TT
AA
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