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參數(shù)資料
| 型號(hào)： | LX1668CDW-TR |
| 廠商： | MICROSEMI CORP-ANALOG MIXED SIGNAL GROUP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1 A SWITCHING CONTROLLER, 250 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | ROHS COMPLIANT, PLASTIC, SOWB-20 |
| 文件頁(yè)數(shù)： | 12/15頁(yè) |
| 文件大?。?/td> | 392K |
| 代理商： | LX1668CDW-TR |
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PROGRAMMABLE MULTIPLE OUTPUT DC:DC CONTROLLER
LX1668
PRODUCT DA T ABOOK 1996/1997
Copyright 1999
Rev. 1.0a
6
P RODUCTION D ATA S HEET
1
TDRV
Gate drive to the top FET.
2V
CC12
+12V supply for the gate drivers. If 12V is not available in the application, a bootstrap circuit is required
to create the biasing voltage for the FET gate drivers.
3V
CC5
+5V supply for internal biasing and power to the IC.
4V
OUT2
Fixed 2.5V internal LDO regulator output.
5V
CC3
Input for the 2.5V internal LDO regulator — Recommended to be connected to 5V.
6L
DRV
Adjustable LDO driver output. Connect to gate of MOSFET.
7L
FB
Voltage feedback pin of the adjustable LDO regulator (1.5V).
8
VID0
Input pins to the DAC. The output of the DAC sets the nominal voltage of the PWM output (see Table 1).
9
VID1
These inputs are TTL-compatible.
10
VID2
11
VID3
12
VID4
13
OVP
Over-voltage protection: this pin is pulled to above 2V when the switcher output is above 17% of its set
voltage. This pin is capable of sourcing 40mA current, and can be used to drive an SCR crowbar or as a
signal to turn off the main power supply.
14
PWRGD
Open collector output, pulled down when the core voltage is not within ±10% of the DAC output or the
fixed 2.5V LDO output is below 2.0V.
15
V
CORE
Output (CPU core) voltage, connected to the output of the regulator (after the sense resistor). This pin is
also connected to the power good and the over current comparators in the IC.
16
V
FB
Dual function pin for feedback and current sensing. The peak voltage of this is set 40mV above the
nominal set-point (VID) voltage. When the voltage difference between this pin and V
OUT (pin 15) exceeds
60mV, the over current comparator will be tripped. The over current tripping level can be set as
I = 60mV/R
SENSE where RSENSE is the sensing resistance (see Application Note section).
17
SS/ENABLE
Soft-startup and hiccup capacitor pin. During startup, the voltage of this pin controls the core voltage. An
internal 20k
resistor and the external capacitor set the time constant for the soft-startup. Soft-start does
not begin until the supply voltage exceeds the UVLO threshold. When over-current occurs, this capacitor is
used for timing the hiccup. See Application Information for more detail. The PWM output can be disabled
by pulling the SS/ENABLE pin below 0.5V.
18
AGND
Analog ground.
19
BDRV
Bottom FET drive.
20
PGND
Power ground. Ground return for FET drivers.
Pin
Number
Designator
Description
FUNCTIONAL PIN DESCRIPTION
O
B
SO
LETE
PRO
D
UCT
NOT
RECOMMENDED
FOR
NEW
DESIGNS
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