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參數(shù)資料
| 型號： | LVXT8051 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | Analog Multiplexer / Demultiplexer High−Performance Silicon−Gate CMOS |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 172K |
| 代理商： | LVXT8051 |
MC74LVXT8051
http://onsemi.com
4
DC ELECTRICAL CHARACTERISTICS
Analog Section
I
V
= V
or V
;
V
IO
= V
CC
or GND;
Switch Off (Figure 3)
5.5
V
4.5
5.5
25
Guaranteed Limit
30
Maximum OffChannel Leakage
Current, Any One Channel
V
IS
= V
CC
to GND
|I
S
|
10.0 mA (Figures 1, 2)
in
IL
IH
|I
S
|
10.0 mA (Figures 1, 2)
V
in
= V
IL
or V
IH
IS
CC
|I
S
|
10.0 mA
5.5
5.5
0.1
1.0
Channels in the Same Package
20
8.0
0.5
32
28
25
12
30
15
37
30
R
on
Maximum Difference in “ON”
Resistance Between Any Two
3.0
15
20
25
A
Maximum OffChannel
Leakage Current,
Common Channel
V
in
= V
IL
or V
IH
;
V
IO
= V
CC
or GND;
Switch Off (Figure 4)
5.5
0.2
2.0
4.0
I
on
Maximum OnChannel
Leakage Current,
ChanneltoChannel
V
in
= V
IL
or V
IH
;
SwitchtoSwitch =
V
CC
or GND; (Figure 5)
5.5
0.2
2.0
4.0
A
AC CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 3 ns)
V
CC
V
Guaranteed Limit
Symbol
Parameter
55 to 25
°
C
≤
85
°
C
≤
125
°
C
Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, ChannelSelect to Analog Output
(Figure 9)
2.0
3.0
4.5
5.5
30
20
15
15
35
25
18
18
40
30
22
20
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
2.0
3.0
4.5
5.5
4.0
3.0
1.0
1.0
6.0
5.0
2.0
2.0
8.0
6.0
2.0
2.0
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0
3.0
4.5
5.5
30
20
15
15
35
25
18
18
40
30
22
20
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0
3.0
4.5
5.5
20
12
8.0
8.0
25
14
10
10
30
15
12
12
ns
C
in
Maximum Input Capacitance, ChannelSelect or Enable Inputs
10
10
10
pF
C
I/O
Maximum Capacitance
Analog I/O
35
35
35
pF
(All Switches Off)
Common O/I
130
130
130
Feedthrough
1.0
1.0
1.0
Typical @ 25
°
C, V
CC
= 5.0 V
45
C
PD
Power Dissipation Capacitance (Figure 13)*
* Used to determine the noload dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
.
pF
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