參數(shù)資料
型號: LVX126
廠商: ON SEMICONDUCTOR
英文描述: Quad Bus Buffe With 5V−Tolerant Inputs
文件頁數(shù): 2/5頁
文件大小: 84K
代理商: LVX126
MC74LVX126
http://onsemi.com
2
Figure 1. 14Lead Pinout
(Top View)
13
14
12
11
10
9
8
2
1
3
4
5
6
7
V
CC
OE3
D3
O3
OE2
D2
O2
OE0
D0
O0
OE1
D1
O1
GND
D0
2
O0
3
OE0
1
D1
5
O1
6
OE1
4
D2
9
O2
8
OE2
10
D3
12
O3
11
OE3
13
Figure 2. Logic Diagram
PIN NAMES
Function
Output Enable Inputs
Data Inputs
3State Outputs
Pins
OEn
Dn
On
H = High Voltage Level; L = Low Voltage Level; Z = High Imped-
ance State; X = High or Low Voltage Level and Transitions Are
Acceptable, for I
CC
reasons, DO NOT FLOAT Inputs
OEn
Dn
On
H
H
L
L
H
X
L
H
Z
INPUTS
OUTPUTS
FUNCTION TABLE
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
±
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage
2.0
3.6
°
C
V
V
in
DC Input Voltage
0
5.5
V
V
out
DC Output Voltage
0
V
CC
V
T
A
Operating Temperature, All Package Types
40
+125
t/ V
Input Rise and Fall Time
0
100
ns/V
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