參數(shù)資料
型號: LV8829LF
廠商: SANYO SEMICONDUCTOR CO LTD
元件分類: 運(yùn)動控制電子
英文描述: BRUSHLESS DC MOTOR CONTROLLER, 1.5 A, QCC24
封裝: 4 X 4 MM, VQFN-24
文件頁數(shù): 2/13頁
文件大?。?/td> 263K
代理商: LV8829LF
LV8829LF
No.A1801-10/13
Description of LV8829LF
1. Output Drive Circuit
This IC adopts a direct PWM drive method to reduce power loss in the output. It regulates the drive force of the motor
by changing the output on duty. The output PWM switching is performed by the upper-side output transistor.
The current regeneration route during the normal PWMOFF passes through the parasitic diode of the output DMOS.
This IC performs synchronous rectification, and is intended to reduce heat generation compared to diode regeneration.
2. Current Limiter Circuit
The current limiter circuit limits the output current peak value to a level determined by the equation I = VRF/Rf (VRF
= 0.21V (typical), Rf: current detection resistor). This circuit suppresses the output current by reducing the output on
duty.
The current limiter circuit has an operation delay (approx. 700ns) to detect reverse recovery current flowing in the
diode due to the PWM operation, and prevent a malfunction of the current limiting operation. If the coil resistance of
the motor is small, or the inductance is low, the current at startup (the state in which there is no back electromotive force
generated in the motor) will change rapidly. As a result, the operation delay may sometimes cause the current limiting
operation to take place at a value above the set current. In such a case, it is necessary to set the current limit value while
taking into consideration the increase in current due to the delay.
* Regarding the PWM frequency in the current limiter circuit
The PWM frequency in the current limiter circuit is determined by the internal reference oscillator, and is
approximately 50kHz.
3. Speed control method
Pulses are input to the PWMIN pin, and the output can be controlled by varying the duty cycle of these pulses.
When a low-level input voltage is applied to the PWMIN pin, the output at the PWM side (upper side) is set to ON.
When a high-level input voltage is applied to the PWMIN pin, the output at the PWM side (upper side) is set to OFF.
If it is necessary to input pulses using inverted logic, this can be done by adding an external transistor (NPN).
When the input to the PWMIN pin remains high-level for a certain period, the IC judges that the duty is 0%, causing the
CSD circuit count to be reset and the output from the HB pin to become low level.
4. Constraint Protection Circuit
The LV8829LF includes a constraint protection circuit for protecting the IC and the motor in a motor constraint mode.
This circuit operates when the motor is in an operation condition and the Hall signal does not switch over for a certain
period. Note that while this constraint protection is operating, the upper-side output transistor will be OFF.
Time setting is performed according to the capacitance of the capacitor connected to the CSD pin.
Set time (s)
≈ 90 × C (μF)
When a 0.022
μF capacitor is connected, the protection time becomes approximately 2.0 seconds. The set time must be
selected to a value that provides adequate margin with respect to the motor startup time.
Conditions for releasing the constraint protection state:
When the S/S pin is in a STOP state
→ Protection released and count reset
When the F/R pin is switched
→ Protection released and count reset
When 0% duty is detected at the PWMIN pin input
→ Protection released and count reset
When low-voltage condition is detected
→ Protection released and count reset (Initial reset)
( When TSD condition is detected
→ Stop counting)
The CSD pin also functions as the initial reset pulse generation pin. If it is connected to ground, the logic circuit will go
into a reset state, preventing speed control from taking place. Consequently, when not using constraint protection,
connect a resistor of approximately 220k
Ω and a capacitor of about 4700pF in parallel to ground.
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