參數(shù)資料
型號: LV8481CS
廠商: SANYO SEMICONDUCTOR CO LTD
元件分類: 運動控制電子
英文描述: STEPPER MOTOR CONTROLLER, PBGA10
封裝: 0.97 X 2.47 MM, 0.50 MM HEIGHT, WLP-10
文件頁數(shù): 10/13頁
文件大?。?/td> 248K
代理商: LV8481CS
LV8481CS
I
2C bus transmission method
Start and stop conditions
The I
2C bus requires that the state of SDA be preserved while SCL is high as shown in the timing diagram below during a
data transfer operation.
ts2
th2
SCL
SDA
When data is not being transferred, both SCL and SDA are in the high state. The start condition is generated and access is
started when SDA is changed from high to low while SCL and SDA are high.
Conversely, the stop condition is generated and access is ended when SDA is changed from low to high while SCL is
high.
th1
th3
SCL
SDA
Start condition
Stop condition
Data transfer and acknowledgement response
After the start condition has been generated, the data is transferred one byte (8 bits) at a time. Generally, in an I
2C bus, a
unique 7-bit slave address is assigned to each device, and the first byte of the transfer data is allocated to the 7-bit slave
address and to the command (R/W) indicating the transfer direction of the subsequent data.
Every time 8 bits of data for each byte are transferred, the ACK signal is sent from the receiving end to the sending end.
Immediately after the clock pulse of SCL bit 8 in the data transferred has fallen to low, SDA at the sending end is released,
and SDA is set to low at the receiving end, causing the ACK signal to be sent.
When, after the receiving end has sent the ACK signal, the transfer of the next byte remains in the receiving status, the
receiving end releases SDA at the falling edge of the ninth SCL clock.
M
S
B
L
S
B
A
C
K
L
S
B
A
C
K
M
S
B
M
S
B
L
S
B
A
C
K
W
Data
RW : 1/0
S7
SCL
SDA
(WRITE)
Data
Slave address
3rd byte
1st byte
Start
Stop
S6 S5 S4 S3 S2 S1 RW
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
Number of Slave Address is 0110010. (S7
→S1)
No.A1600-6/13
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