參數(shù)資料
型號(hào)： LV8414CS
元件分類： 運(yùn)動(dòng)控制電子
英文描述： STEPPER MOTOR CONTROLLER, 0.6 A, PBGA32
封裝： WLP-32
文件頁(yè)數(shù)： 35/36頁(yè)
文件大?。?/td> 451K
代理商： LV8414CS
LV8414CS
No.A1868-8/36
I
2C bus transmission method
Start and stop conditions
The I2C bus requires that the state of SDA be preserved while SCL is high as shown in the timing diagram below during
a data transfer operation.
When data is not being transferred, both SCL and SDA are in the high state. The start condition is generated and access
is started when SDA is changed from high to low while SCL and SDA are high.
Conversely, the stop condition is generated and access is ended when SDA is changed from low to high while SCL is
high.
Data transfer and acknowledgement response
After the start condition is generated, data is transferred one byte (8 bits) at a time. Any number of data bytes can be
transferred consecutively.
An ACK signal is sent to the sending side from the receiving side every time 8 bits of data are transferred. The
transmission of an ACK signal is performed by setting the receiving side SDA to low after SDA at the sending side is
released immediately after the clock pulse of SCL bit 8 in the data transferred has fallen low.
After the receiving side has sent the ACK signal, if the next byte transfer operation is to receive only the byte, the
receiving side releases SDA on the falling edge of the 9th clock of SCL.
There are no CE signals in the I2C bus ; instead, a 7-bit slave address is assigned to each device, and the first byte of the
transfer data is allocated to the 7-bit slave address and to the command (R/W) which specifies the direction of
subsequent data transfer.
The LV8414CS is a drive IC with a dedicated write function and it does not have a read function.
The 7-bit address is transferred in sequence starting with MSB, and the eighth bit is set to low. The second and
subsequent bytes are transferred in write mode.
In the LV8414CS, the slave address is stipulated to be “1110010.”.
ts2
th2
SCL
SDA
th1
ts3
SCL
SDA
Start condition
Stop condition
M
S
B
L
S
B
A
C
K
L
S
B
A
C
K
M
S
B
M
S
B
L
S
B
A
C
K
W
Data
1
SCL
SDA
Data
Slave address
Start
Stop
1100100
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
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