參數(shù)資料
型號(hào): LV8048CS
廠商: SANYO SEMICONDUCTOR CO LTD
元件分類: 運(yùn)動(dòng)控制電子
英文描述: STEPPER MOTOR CONTROLLER, 0.8 A, PBGA36
封裝: 2.87 X 2.47 MM, WLP-36
文件頁數(shù): 26/28頁
文件大?。?/td> 813K
代理商: LV8048CS
LV8048CS
Serial Data Input Overview
Serial Data Input Timing Chart
D0
DATA
SCLK
STB
ST
D1
D2
D3
D4
D5
D6
D7
D8
This edge latches the state setting data.
Data is input in order from D0 to D8. Data is transferred on the SCLK rising edge and, after all data has been transferred,
the data is latched by the rising edge of the STB signal.
Note that the IC internal circuits will not accept the SCLK signal while the STB signal is high.
Timing with which the Serial Data is Reflected in the Outputs
Basically, the new values are reflected in the output at the point the data is latched with the STB signal.
→ Pattern 1
However, the "Excitation direction" and "Excitation mode" settings used in stepping motor clock drive mode for
channels 1 through 4 are an exception. In this case only, after the data is latched with the STB signal, the new values are
reflected on the next rising edge of the CLK1 signal and CLK2 signal.
→ Pattern 2
(Similarly, the “Excitation direction” and “Excitation “mode settings used in the stepping motor clock drive mode for
channels 5 to 6 are also an exception. After the data is latched with the STB signal, the new values are reflected on the
next rising edge of the CLK3 signal.)
[Pattern 1]
[Pattern 2]
CLK
STB
Data latch timing
Rising edge timing
STB timing
CLK
STB
No.A1626-7/28
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