
Method of biasing pin 23
It is necessary to set the DC bias at pin 23 to a value equal to the reference bias of the amplifier through the built-in
LPF. The reference bias of the built-in amplifier is provided by a resistance divider consisting of a 30 k and a 20 k
resistors, and the bias will be about 1.2 V when the power supply voltage is 3 V. As a result, although it is possible to
set the bias of pin 23 using the 30k and 20 k bias resistors, it is recommended to connect a 30 k feedback resistor
between pin 7 and pin 23 (see Fig. 8). Using this biasing method, it is possible to apply the same DC bias as the
internal bias voltage at pin 23 at all times without being affected by variations in the power supply voltage or the
resistance values.
Fig. 8
7. Miscellaneous information
On LOCKDET
This output goes to the high level when the PN code synchronization is achieved. However, since the LOCKDET
sensitivity is lower than the PN synchronization sensitivity, near the input sensitivity limit, even when the demodulated
output is being made, the LOCKDET output may sometimes remain in the low level. Treat this as merely a simple
carrier detection signal.
On ANTDUMP
This is a DC output proportional to the RF input level. However, since the input dynamic range of about 20 dB and the
output range of variation of about 0.5 V are narrow, this output is not suitable for a signal meter. Its major application
is for the saturation prevention circuit of the RF amplifier under strong radio signal inputs.
The lock up time of the reception PLL is about 2 ms to 10 ms at the time of switching on the power, and about 500 μs
to 1ms when there is a change from the no-signal condition to the signal input condition.
8. Recommended Components
No. 5651-15/20
LV2700V
Recommended component
Type No.
Manufacturer
SAW Resonator
SAR 234.74MF10T115
Murata Mfg. Co., Ltd.
236 MHz BPF
LFB30N12B0236B024
Murata Mfg. Co., Ltd.
Variable coil
CS-5N (SA-1100)
Sumida Electric