參數(shù)資料
型號(hào)： LV25450PNW
元件分類(lèi)： 調(diào)諧器
英文描述： AUDIO TUNER, PQFP64
封裝： 10 X 10 MM, SQFP-64
文件頁(yè)數(shù)： 24/40頁(yè)
文件大?。?/td> 1251K
代理商： LV25450PNW
LV25450PNW
No.A1668-30/40
Control Data Documentation
No.
Control block/data
Description
Related data
(1)
Programmable divider data
P0 to P15
DVS
Sets the programmable divider's divisor.
This is a binary value in which P0 is the LSB, P15 the MSB.
DVS = 0 : The IC internal PLL IN pin is stopped (pulled down)
DVS = 1 : The IC internal PLL IN pin is selected
Set divisor (N) : 272 to 65536
Input frequency range : 120 to 270 MHz
* : See the "Programmable Divider Structure" section for more information.
AM/FM
OSC D1, D2
WB, OSC DIV
(2)
AM oscillator divisor control
OSC D1, OSC D2
OSC D1, OSC D2
AM oscillator divisor control
OSC D1
OSC D2
Divisor
0
Divide by 10
0
1
Divide by 8
1
0
Divide by 6
1
Divide by 4
AM/FM
P0 to P15
(3)
Tuner mode switching
AM/FM
Tuner mode switching between AM and FM
1 = AM
0 = FM
P0 to P15
OSC D1, D2
(4)
Programmable divider stop
DVS
DVS = 0 : The IC internal PLL-IN pin is stopped (pulled down)
DVS = 1 : The IC internal PLL-IN pin is selected
Set divisor (N) : 272 to 65536
Input frequency range : 120 to 270 MHz
* : See the "Programmable Divider Structure" section for more information.
(5)
Reference divider data
R0 to R3
Selects the reference frequency.
Reference frequency setting (kHz)
R3
R2
R1
R0
Crystal : 4.5MHz
0
100
0
1
50
0
1
0
25
0
1
25
0
1
0
12.5
0
1
0
1
6.25
0
1
0
3.125
0
1
3.125
1
0
10
1
0
1
9
1
0
1
0
5
1
0
1
0
3
1
0
1
30
1
0
Illegal value
1
Illegal value
Continued on next page.
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