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參數(shù)資料
| 型號(hào)： | LUC4AS01 |
| 廠商： | Lineage Power |
| 英文描述： | ATM Switch Element (ASX)(ATM開(kāi)關(guān)元件) |
| 中文描述： | ATM交換機(jī)元素（澳大利亞）（自動(dòng)柜員機(jī)開(kāi)關(guān)元件） |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大小： | 177K |
| 代理商： | LUC4AS01 |
Lucent Technologies Inc.
3
Advance Product Brief
March 1997
ATM Switch Element (ASX)
LUC4AS01
S
LUCENT TECHNOLOGIES—PROPRIETARY
Use pursuant to Company Instructions
Description
(continued)
The ASX has an internal 512 cell memory, fully shared
across all queues; no external SRAM is required in the
fabric. It supports four delay priorities per queue and
uses a programmable weighted round-robin algorithm
for scheduling delay priority service. Novel techniques
are incorporated for congestion management. An inno-
vative Bell Labs-developed adaptive dynamic threshold
algorithm permits efficient buffer sharing while prevent-
ing any queue from seizing a disproportionate share of
the cell buffer. A novel internal backpressure algorithm
is applied to prevent the fabric cell buffer from overflow-
ing and increase buffer sharing of large-scale buffers
on the port cards using cost-effective, commonly avail-
able SRAMs. The ASX provides efficient unrestricted
multicasting with single copy storage.
The ASX also provides system diagnostic features.
Diagnostic reports include parity errors on inputs, inter-
nal memory overrun errors, and loss of input port
clock. In addition, a CRC is calculated on data input to
the ASX, passed through the ASX, then calculated
after the data is switched to ensure that silicon errors
have not been introduced. When a CRC error is
detected, a parity error is indicated in the data as it is
output from the ASX. Test cell extraction through the
microprocessor interface also aids in testability.
The ASX block diagram and a brief description of the
functionality follows.
5-4515aR9
Figure 2. ASX Block Diagram
INPUT
CLOCKING
AND
26
12
12
12
12
12
12
8 (DATA)
1 (PARITY)
1 (START OF CELL)
2 (CLOCK)
BUFFER MEMORY
(BMEM)
QUEUE
PROCESSOR
(QP)
TEST ACCESS
PORT (JTAG)
OUTPUT
PROCESSOR
12
12
12
12
12
12
12
12
3
5
8 (DATA)
1 (PARITY)
1 (START OF CELL)
2 (CLOCK)
TEST ACCESS
PORT
PROCESSOR
INPUT
PROCESSOR
INPUT
PROCESSOR
INPUT
PROCESSOR
INPUT
PROCESSOR
INPUT
PROCESSOR
INPUT
PROCESSOR
INPUT
PROCESSOR
12
12
ARBITER
(ARB)
OUTPUT
PROCESSOR
OUTPUT
PROCESSOR
OUTPUT
PROCESSOR
OUTPUT
PROCESSOR
OUTPUT
PROCESSOR
OUTPUT
PROCESSOR
OUTPUT
PROCESSOR
EGRESS
PORTS
INGRESS
PORTS
SYNCHRONIZATION
GTSYNC
SYSTEM CLOCK
MICROPROCESSOR
INTERFACE
RESET (GRST)
OUTPUT ENABLE
(ASXOE)
CONFIGURATION AND
STATUS REGISTERS
AND CELL
EXTRACTION FIFO
(MPI)
(GCLK)
FIRST/THIRD STAGE
BACKPRESSURE
(F1T3_1, F1T3_E,
F1T3CLK)
TO ACE
(CB1_m, CB2_n)
SOURCE
8
FEEDBACK
GENERATION CIRCUIT
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