- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384634 > LUC4AC01 (Lineage Power) ATM Crossbar Element (ACE)(ATM縱橫元件（ACE）) PDF資料下載
參數(shù)資料
| 型號： | LUC4AC01 |
| 廠商： | Lineage Power |
| 英文描述： | ATM Crossbar Element (ACE)(ATM縱橫元件（ACE）) |
| 中文描述： | 自動柜員機縱橫元素（ACE）的（自動柜員機縱橫元件（ACE）的） |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 170K |
| 代理商： | LUC4AC01 |
Lucent Technologies Inc.
5
Advance Product Brief
March 1997
ATM Crossbar Element (ACE)
LUC4AC01
S
LUCENT TECHNOLOGIES—PROPRIETARY
Use pursuant to Company Instructions
Description
(continued)
Input Processors
The input processors are responsible for accepting
data into the device. There are eight input processors,
one for each port. Each input port has eight data bits,
one parity bit, one start of cell bit, and a differential
clock. The microprocessor must enable the appropriate
input ports. The input processor shifts data in and
checks parity. Input ports are clocked independently.
The input port interface is designed to minimize the risk
of undetected errors. The differential clock provides
system noise immunity to prevent errors. In addition,
the input processor detects the presence of an input
clock and reports when the input clock is lost. The input
processor also checks for incoming parity errors. Parity
errors and loss of clock are reported through the micro-
processor interface.
Output Processors
The output processors perform the opposite functions
of the input processors. They handle the shifting out of
the data. The microprocessor can disable any output
port.
Source Arbiter
The source arbiter arbitrates access to the crossbar
outputs of the center-stage ACE module. The source
arbiter receives requests from the first-stage ASX mod-
ules. The source arbiter then determines which of
these requests are granted or denied, taking into con-
sideration any output contention in the center-stage or
congestion in the third-stage ASX modules in the
switch fabric.
Microprocessor Interface
The microprocessor interface (MPI) provides a general
16-bit asynchronous interface to an external processor
for accessing the ASX configuration and status regis-
ters and internal memory. The MPI also supports per-
function, maskable interrupts. The interface operates
identically to the interface in the ALM, ABM, and ASX.
The MPI is designed to support various 16-bit micro-
processors with minimal glue logic, and to directly inter-
face to popular
Intel
and
Motorola
microprocessors.
Test Access Port
The ACE incorporates logic to support a standard five-
pin test access port (TAP), compatible with the
P1149.1 standard (JTAG), used for boundary scan.
TAP contains instruction registers, data registers, and
control logic, and has its own set of instructions. It is
controlled externally by a JTAG bus master. The TAP
gives the ACE board-level test capability.
IEEE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LUC4AS01 | ATM Switch Element (ASX)(ATM開關(guān)元件) |
| LUC4AU01 | ATM Layer UNI Manager (ALM)(ATM 層UNI管理器(ALM)) |
| LVSP60 | Blade Terminal & Special Purpose Fuses - Surge Fuses |
| LVSP80 | Blade Terminal & Special Purpose Fuses - Surge Fuses |
| LVSP20 | Blade Terminal & Special Purpose Fuses - Surge Fuses |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LUC4AS01-BC7-DB | 制造商:Agere Systems 功能描述: |
| LUC4AU01SC5DB | 制造商:LUCENT 功能描述:* |
| LUC4AU01-SC5-DB | 制造商:Agere Systems 功能描述: |
| LUC4AU01-SC6 | 制造商:Alcatel-Lucent 功能描述: 制造商:LUCENT 功能描述: |
| LUC4AU01-SC6-DB | 制造商:Alcatel-Lucent 功能描述:Electronic Component |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。