參數(shù)資料
型號(hào)： LU5X34F
廠商： Lineage Power
英文描述： Quad Gigabit Ethernet Transceiver(千兆位以太網(wǎng)四收發(fā)器)
中文描述： 四個(gè)千兆以太網(wǎng)收發(fā)器（千兆位以太網(wǎng)四收發(fā)器）
文件頁(yè)數(shù)： 1/26頁(yè)
文件大?。?/td> 445K
代理商： LU5X34F
Preliminary Data Sheet
July 2000
LU5X34F
Quad Gigabit Ethernet Transceiver
Overview
The LU5X34F is a low-cost, low-power quad trans-
ceiver. It is used for data transmission over fiber or
coaxial media in conformance with IEEE
* 802.3z
Gigabit Ethernet specification and Fibre Channel
ANSI
X3T11 at 1.0 Gbits/s and
1.25 Gbits/s.
Each of the four transceivers independently provides
complete serialize/deserialize (SERDES) and trans-
mit and receive functions. The device is available in a
217-pin PBGA package.
The transmitter section accepts TTL compatible data
at the 10-bit parallel input port. The parallel input
data is latched on the rising edge of TXCLKx. It also
accepts the low-speed, TTL compatible system
clock, REFCLK, and uses this clock to synthesize the
internal high-speed serial bit clock. The serialized
data is then available at the differential PECL out-
puts, terminated in 50
or 75
to drive either an
optical transmitter or coaxial media.
The receive section receives high-speed serial data
at its differential PECL input port. This data is fed to
the digital clock recovery section, which generates a
recovered clock and retimes the data. The retimed
data is deserialized and presented as 10-bit parallel
data on the output port. A divided-down version of
the recovered clock, synchronous with parallel data
bytes, is also available as a TTL compatible output.
The receive section recognizes the comma character
and aligns the comma-containing byte on the word
boundary, when ENCDET = 1.
Features
I
Designed to operate in Ethernet, fibre channel,
Firewire
, or backplane applications.
I
Operationally compliant to IEEE 802.3z Gigabit
Ethernet specification.
I
Operationally compliant to Fibre Channel ANSI
X3T11. Provides FC-0 services at 1.0 Gbits/s—
1.25 Gbits/s (10-bit encoded data rate).
I
100 MHz—125 MHz differential or single-ended
reference clock.
I
10-bit parallel, TTL-compatible I/O interface.
I
8-bit/10-bit encoded data.
I
High-speed comma character recognition (K28.1,
K28.5, K28.7) for latency-sensitive applications
and alignment to word boundary.
I
Two 50 MHz—62.5 MHz receive-byte clocks.
I
Single analog PLL design requires no external
components for the frequency synthesizer.
I
Novel digital data lock in receiver avoids the need
for multiple analog PLLs.
I
Expandable beyond four serializer/deserializers.
I
PECL high-speed interface I/O for use with optical
transceiver or coaxial copper media.
I
Requires one external resistor for PECL output ref-
erence-level definition.
I
Low-power digital CMOS technology.
I
Less than 2 W total power dissipation per quad
transceiver.
I
3.3 V ± 5% power supply.
I
0 °C—70 °C ambient temperature.
I
Stand-alone transceiver product.
I
Transceiver macrocell template.
I
Available in 217-pin PBGA package.
* IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
ANSI is a registered trademark of American National Standards
Institute.
FireWireis a registered trademark of Apple Computer, Inc.
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