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參數(shù)資料
| 型號： | LU3X31T-T64 |
| 英文描述： | LU3X31T-T64 Single-Port 3 10/100 Ethernet Transceiver TX |
| 中文描述： | LU3X31T - T64單端口10/100以太網(wǎng)收發(fā)器3得克薩斯州 |
| 文件頁數(shù)： | 6/44頁 |
| 文件大?。?/td> | 580K |
| 代理商： | LU3X31T-T64 |
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LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
6
Lucent Technologies Inc.
Pin Descriptions
Table 2. Twisted-Pair Transceiver Control
Table 3. MII Interface
Note: Smaller font indicates that the pin has multiple functions.
Pin
No.
50
Pin Name
I/O
Pin Description
REF100
I
Reference Resistor for 100 Mbits/s Twisted-Pair Driver.
Connect
this pin to ground through a 301
resistor.
Reference Resistor for 10 Mbits/s Twisted-Pair Driver.
Connect
this pin to ground through a 4.64 k
resistor.
Twisted-Pair Transmitter 3-State.
A high on this pin will 3-state the
twisted-pair outputs. Tie to ground in normal operation.
49
REF10
I
5
TPTXTR
I
Pin
No.
18
19
20
21
22
23
24
27
28
29
30
31
32
33
34
Pin Name
I/O
Pin Description
RXDV
RXER
RXD3
RXD2
RXD1
RXD0
RXCLK
TXEN
TXER
TXD3
TXD2
TXD1
TXD0
TXCLK
CRS/
PHY[3]
O
O
O
O
O
O
O
I
I
I
I
I
I
O
I/O
Receive Data Valid.
Signals the presence of data on RXD[3:0].
Receive Error.
Indicates a received coding error has occurred.
Receive Data[3].
Receive Data[2].
Receive Data[1].
Receive Data[0].
Receive Clock.
Transmit Enable.
Signals the presence of data on TXD[3:0].
Transmit Error.
Indicates a transmit coding error has occurred.
Transmit Data[3].
Transmit Data[2].
Transmit Data[1].
Transmit Data[0].
Transmit Clock.
Carrier Sense/PHY Address[3].
This output pin indicates the carrier
sense condition. See Table 4 for PHY[3] description.
Collision/False Carrier Sense.
This output pin indicates collision
condition in normal MII operation and is squelch jabber in 10 Mbits/s
mode. See Table 4 for PHY[4] description.
Management Data I/O.
Serial access to device config registers.
Management Data Clock.
Clock for R/W of device config registers.
MDIO Interrupt (Active-Low).
The MDIO interrupt pin outputs a logic
0 pulse of 40 ns, synchronous to XIN, whenever an unmasked inter-
rupt condition is detected. Refer to management registers 1Dh and
1Eh for interrupt conditions. See Table 4 for PHY[2] description.
39
COL/
PHY[4]
I/O
35
45
16
MDIO
MDC
I/O
I
I/O
MDIOINTZ/
PHY[2]
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