參數(shù)資料
型號(hào): LTM4601AHVY
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: SWITCHING REGULATOR, PBGA133
封裝: 15 X 15 MM, 2.82 MM HEIGHT, LEAD FREE, LGA-133
文件頁(yè)數(shù): 6/30頁(yè)
文件大?。?/td> 519K
代理商: LTM4601AHVY
LTM4601AHV
14
4601ahvfb
Run Enable
The RUN pin is used to enable the power module. The
pin has an internal 5.1V Zener to ground. The pin can be
driven with a logic input not to exceed 5V.
The RUN pin can also be used as an undervoltage lock out
(UVLO) function by connecting a resistor divider from the
input supply to the RUN pin:
VUVLO =
R1
+R2
R2
1.5V
See Figure 1, Simplified Block Diagram.
Power Good
The PGOOD pin is an open-drain pin that can be used to
monitor valid output voltage regulation. This pin monitors
a ±10% window around the regulation point and tracks
with margining.
COMP Pin
This pin is the external compensation pin. The module
has already been internally compensated for most output
voltages. Table 2 is provided for most application require-
ments. LTpowerCAD is available for other control loop
optimization.
PLLIN
The power module has a phase-locked loop comprised
of an internal voltage controlled oscillator and a phase
detector. This allows the internal top MOSFET turn-on
to be locked to the rising edge of an external clock. The
frequency range is ±30% around the operating frequency
of 850kHz. A pulse detection circuit is used to detect a
clock on the PLLIN pin to turn on the phase-locked loop.
The pulse width of the clock has to be at least 400ns and
the amplitude at least 2V. The PLLIN pin must be driven
from a low impedance source such as a logic gate located
closetothepin.Duringstart-upoftheregulator,thephase-
locked loop function is disabled.
INTVCC and DRVCC Connection
An internal low dropout regulator produces an internal
5V supply that powers the control circuitry and DRVCC
for driving the internal power MOSFETs. Therefore, if the
system does not have a 5V power rail, the LTM4601AHV
can be directly powered by VIN. The gate drive current
through the LDO is about 20mA. The internal LDO power
dissipation can be calculated as:
PLDO_LOSS = 20mA (VIN – 5V)
The LTM4601AHV also provides the external gate drive
voltage pin DRVCC. If there is a 5V rail in the system, it is
recommended to connect the DRVCC pin to the external
5V rail. This is especially true for higher input voltages. Do
not apply more than 6V to the DRVCC pin. A 5V output can
be used to power the DRVCC pin with an external circuit
as shown in Figure 18.
Parallel Operation of the Module
The LTM4601AHV device is an inherently current mode
controlled device. Parallel modules will have very good
current sharing. This will balance the thermals on the de-
sign. Figure 21 shows the schematic of a parallel design.
The voltage feedback equation changes with the variable
n as modules are paralleled:
VOUT = 0.6V
60.4k
N
+ RSET
RSET
or equivalently:
RSET =
60.4k
N
VOUT
0.6V
1
where N is the number of paralleled modules.
Figure 21 shows two LTM4601AHV modules used in a
parallel design. An LTM4601AHV device can be used
without the differential amplifier.
applicaTions inForMaTion
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