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參數(shù)資料
| 型號： | LTCZS |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 16-/14-/12-Bit VOUT DACs in 3mm 】 3mm DFN |
| 中文描述： | 16/14/12 VOUT電源數(shù)模轉(zhuǎn)換器采用3mm DFN封裝】3毫米 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 317K |
| 代理商： | LTCZS |
LTC2641/LTC2642
10
26412f
BLOCK DIAGRAMS
16-BIT DATA LATCH
CONTROL
LOGIC
16-/14-/12-BIT DAC
V
DD
REF
V
OUT
GND
8
2641 BD
16-BIT SHIFT REGISTER
POWER-ON
RESET
LTC2641-16
LTC2641-14
LTC2641-12
CS
SCLK
DIN
CLR
6
5
4
3
2
1
7
16-BIT DATA LATCH
CONTROL
LOGIC
16-/14-/12-BIT DAC
INV
R
FB
V
DD
REF
V
OUT
GND
10
2642 BD
16-BIT SHIFT REGISTER
POWER-ON
RESET
LTC2642-16
LTC2642-14
LTC2642-12
CS
SCLK
DIN
CLR
8
7
6
5
4
3
2
1
9
LTC2641
LTC2642
TIMING DIAGRAM
t
1
SCK
SDI
CS/LD
t
5
t
7
t
2
t
6
t
8
26412 TD
1
2
3
15
16
t
3
t
4
OPERATION
General Description
The LTC2641/LTC2642 family of 16-/14-/12-bit voltage
output DACs offer full 16-bit performance with less than
±2LSB integral linearity error and less than ±1LSB differen-
tial linearity error, guaranteeing monotonic operation. They
operate from a single supply ranging from 2.7V to 5.5V,
consuming 120μA (typical). An external voltage reference
of 2V to V
DD
determines the DAC’s full-scale output volt-
age. A 3-wire serial interface allows the LTC2641/LTC2642
to fit into a small 8-/10-pin MSOP or DFN 3mm
×
3mm
package.
Digital-to-Analog Architecture
The DAC architecture is a voltage switching mode resis-
tor ladder using precision thin-film resistors and CMOS
switches. The LTC2641/LTC2642 DAC resistor ladders are
composed of a proprietary arrangement of matched DAC
sections. The four MSBs are decoded to drive 15 equally
weighted segments, and the remaining lower bits drive
successively lower weighted sections. Major carry glitch
impulse is very low at 500pVsec, C
L
= 10pF, ten times
lower than previous DACs of this type.
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