- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9306 > LTC6994CS6-2#TRMPBF (Linear Technology)IC DELAY LINE TSOT-23-6 PDF資料下載
參數(shù)資料
| 型號： | LTC6994CS6-2#TRMPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE TSOT-23-6 |
| 產(chǎn)品培訓(xùn)模塊： | TimerBlox Family Timing Devices |
| 產(chǎn)品目錄繪圖： | LTC699_TSOT-23 |
| 特色產(chǎn)品： | TimerBlox? |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TimerBlox® |
| 功能： | 可編程 |
| 可用的總延遲： | 1µs ~ 33.6s |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 2.25 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 細(xì)型，TSOT-23-6 |
| 供應(yīng)商設(shè)備封裝： | TSOT-23-6 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 配用： | DC1562A-E-ND - BOARD EVAL LTC6992-3 |
| 其它名稱： | LTC6994CS6-2#TRMPBFDKR |
第1頁第2頁當(dāng)前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁
LTC6994-1/LTC6994-2
11
699412fb
operaTion
The LTC6994 is built around a master oscillator with a 1s
minimum period. The oscillator is controlled by the SET
pin current (ISET) and voltage (VSET), with a 1s/50kΩ
conversion factor that is accurate to ±1.7% under typical
conditions.
tMASTER =
1s
50k
VSET
ISET
A feedback loop maintains VSET at 1V ±30mV, leaving ISET
as the primary means of controlling the input-to-output
delay. The simplest way to generate ISET is to connect a
resistor (RSET) between SET and GND, such that ISET =
VSET/RSET. The master oscillator equation reduces to:
tMASTER =1s
RSET
50k
From this equation, it is clear that VSET drift will not affect
the input-to-output delay when using a single program
resistor (RSET). Error sources are limited to RSET toler-
ance and the inherent accuracy
tDELAY of the LTC6994.
RSET may range from 50k to 800k (equivalent to ISET
between 1.25A and 20A).
When the input makes a transition that will be delayed
(as determined by the part version and POL bit setting),
the master oscillator is enabled to time the delay. When
the desired duration is reached, the output is allowed to
transition.
The LTC6994 also includes a programmable frequency
divider which can further divide the frequency by 1, 8, 64,
512, 4096, 215, 218 or 221. This extends the delay duration
by those same factors. The divider ratio NDIV is set by a
resistor divider attached to the DIV pin.
tDELAY =
NDIV
50k
VSET
ISET
1s
With RSET in place of VSET/ISET the equation reduces to:
tDELAY =
NDIV RSET
50k
1s
DIVCODE
TheDIVpinconnectstoaninternal,V+referenced4-bitA/D
converter that determines the DIVCODE value. DIVCODE
programs two settings on the LTC6994:
1. DIVCODE determines the frequency divider setting,
NDIV.
2. The DIVCODE MSB is the POL bit, and configures a
different polarity setting on the two versions.
a. LTC6994-1:POLselectsrisingorfalling-edgedelays.
POL = 0 will delay rising-edge transitions. POL = 1
will delay falling-edge transitions.
b. LTC6994-2: POL selects the output inversion.
POL = 1 inverts the output signal.
VDIV may be generated by a resistor divider between V+
and GND as shown in Figure 1.
699412 F01
LTC6994
V+
DIV
GND
R1
R2
2.25V TO 5.5V
Figure 1. Simple Technique for Setting DIVCODE
Table 1 offers recommended 1% resistor values that ac-
curately produce the correct voltage division as well as the
corresponding NDIVandPOLvaluesfortherecommended
resistor pairs. Other values may be used as long as:
1. The VDIV/V+ ratio is accurate to ±1.5% (including resis-
tor tolerances and temperature effects)
2. Thedrivingimpedance(R1||R2)doesnotexceed500kΩ.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-BW3-MW-B1 | CONVERTER MOD DC/DC 24V 100W |
| VI-B40-IU-F1 | CONVERTER MOD DC/DC 5V 200W |
| MS27472E20F35S | CONN RCPT 79POS WALL MNT W/SCKT |
| AD5170BRMZ50-RL7 | IC DGTL POT 256POS 50K 10MSOP |
| M83723/85R1610N | CONN RCPT 10POS JAM NUT W/PINS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC6994HDCB-1#PBF | 制造商:Linear Technology 功能描述:SC-Timing, Cut Tape Delay with Rising or Falling Edge Trigger |
| LTC6994HDCB-1#TRMPBF | 功能描述:IC DELAY LINE 6-DFN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 延遲線 系列:TimerBlox® 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級數(shù):- 功能:多個(gè)，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨(dú)立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
| LTC6994HDCB-1#TRPBF | 功能描述:IC DELAY LINE 6-DFN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 延遲線 系列:TimerBlox® 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級數(shù):- 功能:多個(gè)，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨(dú)立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
| LTC6994HDCB-1TRMPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:TimerBlox: Delay Block/ Debouncer |
| LTC6994HDCB-2#TRMPBF | 功能描述:IC DELAY LINE 6-DFN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 延遲線 系列:TimerBlox® 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級數(shù):- 功能:多個(gè)，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨(dú)立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。