- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2007 > LTC6994CDCB-2#TRPBF (Linear Technology)IC DELAY LINE 6-DFN PDF資料下載
參數(shù)資料
| 型號： | LTC6994CDCB-2#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 10/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 6-DFN |
| 產(chǎn)品培訓(xùn)模塊： | TimerBlox Family Timing Devices |
| 產(chǎn)品目錄繪圖： | LTC699_DFN |
| 特色產(chǎn)品： | TimerBlox? |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | TimerBlox® |
| 功能： | 可編程 |
| 可用的總延遲： | 1µs ~ 33.6s |
| 獨立延遲數(shù)： | 1 |
| 電源電壓： | 2.25 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 6-DFN-EP（2x3） |
| 包裝： | 帶卷 (TR) |
| 配用： | DC1562A-E-ND - BOARD EVAL LTC6992-3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁
LTC6994-1/LTC6994-2
18
699412fb
applicaTions inForMaTion
Settling Time
Following a 2
× or 0.5× step change in ISET, the out-
put delay takes approximately six master clock cycles
(6 tMASTER) to settle to within 1% of the final value.
An example is shown in Figure 12, using the circuit in
Figure 10.
Figure 12. Typical Settling Time
VCTRL
2V/DIV
IN
5V/DIV
OUT
5V/DIV
DELAY
2s/DIV
LTC6994-1
V+ = 3.3V
DIVCODE = 0
RSET = 200k
RMOD = 464k
tOUT = 3s AND 6s
20s/DIV
699412 F12
Coupling Error
The current sourced by the SET pin is used to bias the
internal master oscillator. The LTC6994 responds to
changesinISETalmostimmediately,whichprovidesexcel-
lent settling time. However, this fast response also makes
the SET pin sensitive to coupling from digital signals, such
as the IN input.
Even an excellent layout will allow some coupling between
IN and SET. Additional error is included in the specified
accuracy for NDIV = 1 to account for this. Figure 13 shows
that ÷1 supply variation is dependent on coupling from
rising or falling inputs.
A very poor layout can actually degrade performance
further. The PCB layout should avoid routing SET next to
IN (or any other fast-edge, wide-swing signal).
SUPPLY (V)
2
–1.0
0
0.4
0.2
0.6
0.8
1.0
4
5
6
–0.4
–0.2
–0.6
–0.8
3
699412 F13
DRIFT
(%)
FALLING EDGE DELAY
RISING EDGE DELAY
RSET = 50k
NDIV = 1
Figure 13. Delay Drift vs Supply Voltage
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC7541ABN#PBF | IC CMOS D/A CONV 12BIT 18-DIP |
| LTC7545ACG#TRPBF | IC D/ACONV MULTIPLY 12BIT 20SSOP |
| LTC8043EN8 | IC D/A CONV 12BIT SERIAL 8-DIP |
| LTC8143ESW#TRPBF | IC D/A CONV 12BIT SERIAL 16-SOIC |
| LTM9011CY-14#PBF | IC ADC 14BIT UMODULE 140BGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC6994CS6-1#PBF | 制造商:Linear Technology 功能描述:SC-Timing, Cut Tape Delay with Rising or Falling Edge Trigger |
| LTC6994CS6-1#TRMPBF | 功能描述:IC DELAY LINE TSOT-23-6 RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 延遲線 系列:TimerBlox® 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級數(shù):- 功能:多個，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
| LTC6994CS6-1#TRPBF | 功能描述:IC DELAY LINE TSOT-23-6 RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 延遲線 系列:TimerBlox® 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級數(shù):- 功能:多個，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
| LTC6994CS6-1TRMPBF | 制造商:Linear Technology 功能描述:Delay Block/Debouncer 1us-33.6s TSOT23-6 |
| LTC6994CS6-2#PBF | 制造商:Linear Technology 功能描述:DELAY BLOCK/DEBOUNCER 5.5V T 制造商:Linear Technology 功能描述:DELAY BLOCK/DEBOUNCER, 5.5V, TSOT-23-6; Operating Mode:Monostable; Supply Voltage Min:2.25V; Supply Voltage Max:5.5V; Digital IC Case Style:TSOT-23; No. of Pins:6; Clock External Input:Yes; Operating Temperature Min:0C ;RoHS Compliant: Yes |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。