參數(shù)資料
型號(hào)： LTC6992MPS6-4#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 8/34頁(yè)
文件大小： 0K
描述： IC OSC PWM VOLT CTLR TSOT23-6
特色產(chǎn)品： TimerBlox?
標(biāo)準(zhǔn)包裝： 2,500
系列： TimerBlox®
類型： 振蕩器 - 硅
頻率： 3.81Hz ~ 1MHz
電源電壓： 2.25 V ~ 5.5 V
電流 - 電源： 365µA
工作溫度： -55°C ~ 125°C
封裝/外殼： SOT-23-6 細(xì)型，TSOT-23-6
包裝： 帶卷 (TR)
供應(yīng)商設(shè)備封裝： TSOT-23-6
安裝類型： 表面貼裝
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
16
69921234fc
Pulse Width (Duty Cycle) Modulation
The MOD pin is a high impedance analog input providing
direct control of the output duty cycle. The duty cycle is
proportional to the voltage applied to the MOD pin, VMOD.
Duty Cycle = D =
VMOD
0.8 VSET
1
8
The PWM duty cycle accuracy
D specifies that the above
equation is valid to within ±4.5% for VMOD between 0.2
VSET and 0.8 VSET (12.5% to 87.5% duty cycle).
Since VSET = 1V ±30mV, the duty cycle equation may be
approximated by the following equation.
Duty Cycle = D
VMOD 100mV
800mV
The VMOD control range is approximately 0.1V to 0.9V.
Driving VMOD beyond that range (towards GND or V+) will
have no further affect on the duty cycle.
Duty Cycle Limits
The only difference between the four versions of the
LTC6992 is the limits, or clamps, placed on the output
duty cycle. The LTC6992-1 generates output duty cycles
ranging from 0% to 100%. At 0% or 100% the output
will stop oscillating and rest at GND or V+, respectively.
The LTC6992-2 will never stop oscillating, regardless of
the VMOD level. Internal clamping circuits limit its duty
cycle to a 5% to 95% range (1% to 99% guaranteed).
Therefore, its VMOD control range is 0.14 VSET to 0.86
VSET (approximately 0.14V to 0.86V).
The LTC6992-3 and LTC6992-4 complete the family by
providing one-sided clamping. The LTC6992-3 allows
0% to 95% duty cycle, and the LTC6992-4 allows 5% to
100% duty cycle.
Output Polarity (POL Bit)
The duty cycle equation describes a proportional transfer
function, where duty cycle increases as VMOD increases.
The LTC6992 includes a POL bit (determined by the
DIVCODE as described earlier) that inverts the output
signal. This makes the duty cycle gain negative, reducing
duty cycle as VMOD increases.
operaTion
Figure 3. POL Bit Functionality
6992 F03
OUT
POL = 1
tOUT
DtOUT
OUT
POL = 0
tOUT
DtOUT
D
=
VMOD
0.8 VSET
1
8
D
= 1
VMOD
0.8 VSET
1
8
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