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參數(shù)資料
| 型號(hào)： | LTC6990CDCB#TRMPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 25/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OSC SILICON 1MHZ 6DFN |
| 產(chǎn)品培訓(xùn)模塊： | TimerBlox Family Timing Devices |
| 特色產(chǎn)品： | TimerBlox? |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TimerBlox® |
| 類型： | 振蕩器 - 硅 |
| 頻率： | 488Hz ~ 1MHz |
| 電源電壓： | 2.25 V ~ 5.5 V |
| 電流 - 電源： | 235µA |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 6-WFDFN 裸露焊盤 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 供應(yīng)商設(shè)備封裝： | 6-DFN-EP（2x3） |
| 安裝類型： | 表面貼裝 |
| 配用： | DC1562A-A-ND - BOARD EVAL LTC6990 |
| 其它名稱： | LTC6990CDCB#TRMPBFDKR |
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LTC6990
4
6990fc
For more information www.linear.com/LTC6990
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, OE = V+, DIVCODE = 0 to 15
(NDIV = 1 to 128), RSET = 25k to 800k, RLOAD = ∞, CLOAD = 5pF unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6990C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 3: The LTC6990C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6990C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but it is not tested or
QA sampled at these temperatures. The LTC6990I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6990H is guaranteed
to meet specified performance from –40°C to 125°C. The LTC6990MP is
guaranteed to meet specified performance from –55°C to 125°C.
Note 4: Frequency accuracy is defined as the deviation from the fOUT
equation, assuming RSET is used to program the frequency.
Note 5: See Operation section, Table 1 and Figure 2 for a full explanation
of how the DIV pin voltage selects the value of DIVCODE.
Note 6: The OE pin has hysteresis to accommodate slow rising or falling
signals. The threshold voltages are proportional to V+. Typical values can
be estimated at any supply voltage using VOE(RISING) ≈ 0.55 V+ + 185mV
and VOE(FALLING) ≈ 0.48 V+ – 155mV.
Note 7: To conform to the Logic IC Standard, current out of a pin is
Note 8: Output rise and fall times are measured between the 10% and the
90% power supply levels with 5pF output load. These specifications are
based on characterization.
Note 9: Settling time is the amount of time required for the output to settle
within ±1% of the final frequency after a 0.5x or 2x change in ISET.
Note 10: Jitter is the ratio of the deviation of the period to the mean of the
period. This specification is based on characterization and is not 100% tested.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital I/O
OE Pin Input Capacitance
2.5
pF
OE Pin Input Current
OE = 0V to V+
l
±10
nA
VIH
High Level OE Pin Input Voltage
(Note 6)
l
0.7V+
V
VIL
Low Level OE Pin Input Voltage
(Note 6)
l
0.3V+
V
OUT Pin Hi-Z Leakage
OE = 0V, DIVCODE ≥ 8, OUT = 0V to V+
±10
A
IOUT(MAX)
Maximum Output Current
±20
mA
VOH
High Level Output Voltage
(Note 7)
V+ = 5.5V
IOH = –1mA
IOH = –16mA
l
5.45
4.84
5.48
5.15
V
V+ = 3.3V
IOH = –1mA
IOH = –10mA
l
3.24
2.75
3.27
2.99
V
V+ = 2.25V
IOH = –1mA
IOH = –8mA
l
2.17
1.58
2.21
1.88
V
VOL
Low Level Output Voltage
(Note 7)
V+ = 5.5V
IOL = 1mA
IOL = 16mA
l
0.02
0.26
0.04
0.54
V
V+ = 3.3V
IOL = 1mA
IOL = 10mA
l
0.03
0.22
0.05
0.46
V
V+ = 2.25V
IOL = 1mA
IOL = 8mA
l
0.03
0.26
0.07
0.54
V
tPD
Output Disable Propagation Delay V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
17
26
44
ns
tENABLE
Output Enable Time
NDIV ≤ 2, tOUT = 1/fOUT
NDIV ≥ 4, tMASTER = tOUT/NDIV
tPD to tOUT
tPD to 2tMASTER
s
tr
Output Rise Time (Note 8)
V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
1.1
1.7
2.7
ns
tf
Output Fall Time (Note 8)
V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
1.0
1.6
2.4
ns
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