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參數(shù)資料
| 型號： | LTC6946IUFD-3#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTEGER-N PLL W/VCO 28-QFN |
| 軟件下載： | PLLWizard™ PLLWizard™, with .NET 2.0 installer |
| 標準包裝： | 73 |
| 類型： | 時鐘/頻率合成器（RF/IF），分數(shù)-N，整數(shù)-N， |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 5.79GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.15 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-QFN（4x5） |
| 包裝： | 管件 |
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LTC6946
13
6946fa
divide ratio. See the Applications Information section for
the relationship between R and the fREF, fPFD, fVCO and
fRF frequencies.
PHASE/FREQUENCY DETECTOR (PFD)
The phase/frequency detector (PFD), in conjunction with
the charge pump, produces source and sink current pulses
proportional to the phase difference between the outputs
of the R and N dividers. This action provides the necessary
feedback to phase-lock the loop, forcing a phase align-
ment at the PFD’s inputs. The PFD may be disabled with
the CPRST bit which prevents UP and DOWN pulses from
being produced. See Figure 3 for a simplified schematic
of the PFD.
The BST bit should be set based upon the input signal level
to prevent the reference input buffer from saturating. See
Table 2 for recommended settings and the Applications
Information section for programming examples.
Table 1. FILT[1:0] Programming
FILT[1:0]
fREF
3
<20MHz
2NA
1
20MHz to 50MHz
0
>50MHz
Table 2. BST Programming
BST
VREF
1
<2.0VP-P
0
≥2.0VP-P
REFERENCE OUTPUT BUFFER
The reference output buffer produces a low noise square
wave with a noise floor of –155dBc/Hz (typical) at 10MHz.
Its output is low impedance, and produces 0dBm typical
output power into a 50Ω load at 10MHz. Larger output
swings will result if driving larger impedances. The out-
put is self-biased, and must be AC-coupled with a 22nF
capacitor (see Figure 2 for a simplified schematic). The
buffer may be powered down by using bit PDREFO found
in the serial port Power register h02.
2
REFO
VREFO
+
800Ω
6946 F02
Figure 2. Simplified REFO Interface Schematic
OPERATION
DQ
RST
N DIV
DQ
RST
CPRST
UP
DOWN
6946 F03
DELAY
R DIV
Figure 3. Simplified PFD Schematic
REFERENCE (R) DIVIDER
A 10-bit divider, R_DIV, is used to reduce the frequency
seen at the PFD. Its divide ratio R may be set to any
integer from 1 to 1023, inclusive. Use the RD[9:0] bits
found in registers h03 and h04 to directly program the R
LOCK INDICATOR
The lock indicator uses internal signals from the PFD to
measure phase coincidence between the R and N divider
output signals. It is enabled by setting the LKEN bit in
the serial port register h07, and produces both LOCK and
UNLOCK status flags, available through both the STAT
output and serial port register h00.
The user sets the phase difference lock window time,
tLWW, for a valid LOCK condition with the LKWIN[1:0] bits.
See Table 3 for recommended settings for different FPFD
frequencies and the Applications Information section for
examples.
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