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參數(shù)資料
| 型號： | LTC6909HMS#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OSC SILICON 6.67MHZ 16-MSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 振蕩器 - 硅 |
| 頻率： | 12.5kHz ~ 6.67MHz |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電流 - 電源： | 2.4mA |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 16-TFSOP（0.118"，3.00mm 寬） |
| 包裝： | 帶卷 (TR) |
| 供應(yīng)商設(shè)備封裝： | 16-MSOP |
| 安裝類型： | 表面貼裝 |
LTC6909
14
6909fa
peakelectromagneticradiation(orconduction)isreduced.
Outputripplemaybesomewhatincreased,butitsbehavior
is very much like noise and its system impact is benign.
SUPPLY BYPASSING, SIGNAL CONNECTIONS AND
PCB LAYOUT
Using the LTC6909 in spread spectrum mode naturally
eliminates any concerns for output frequency accuracy
and stability as it is continually hopping to new settings.
In fixed frequency applications however, some attention to
V+ supply voltage ripple is required to minimize additional
output frequency error. Ripple frequency components on
the supply line near the programmed output frequency of
the LTC6909 in excess of 30mVP-P could create an addi-
tional0.2%offrequencyerror.Inapplicationswhereafixed
frequency LTC6909 output clock is used to synchronize
the same switching regulator that provides the V+ supply
to the oscillator, noticeable jitter of the clock may occur if
the ripple exceeds 30mVP-P .
The LTC6909’s accuracy is affected as described above
by supply ripple on the V+A pin only. The V+D pin is es-
sentially insensitive to supply ripple. The V+A pin supplies
the power for the analog section of the LTC6909 and its
current is largely constant for a given RSET resistor value.
The V+D pin supplies the digital section including the out-
put drivers and its current requirement consists mainly of
large bursts that digital circuitry requires when switching.
The peak current required by the output drivers is by far
the largest. The current is mainly dependent on output
capacitive loading and the supply voltage.
Figure 6 shows how to connect the V+A and V+D supply
pinstothepowersupplyaswellasasuggestedPCBlayout.
The PCB layout assumes a two layer board with a ground
plane in the layer beneath the part and 0805 sized passive
components. The PCB layout in Figure 6 is a guide and
need not be followed exactly. However, there are several
items to note from the layout as follows:
1. There should be a ground plane underneath and around
the part. Connect the GND pin to this plane through
multiple (three to four minimum) vias to minimize
inductance.
2. Place the bypass capacitors, C1 and C2, as close to the
V+AandV+Dpinsaspossibletominimizetheinductance
between the capacitor’s lead and the part’s pins.
3. The connection to the V+A and V+D pins to the main
supply should be through a low impedance path. If
the board has a V+ power plane, use it instead of the
top layer connection shown in Figure 6. Use multiple
vias (three to four minimum) at each point to connect
the V+A and V+D pins to the V+ plane to minimize the
inductance.
4.Connectthebypasscapacitors,C1andC2,directlytothe
GND pin using a low inductance path. The connection
from C1 to the GND pin is easily done directly on the top
layer. The C2 path is more difficult but is accomplished
through multiple vias to the ground plane.
5. Connect the RSET resistor directly to the SET pin and
the V+A pin. Connecting the resistor to the V+ supply
through any manner other than directly to the V+A pin
will result greater frequency error.
6. Provide a ground shield around the RSET resistor and
its connections to V+A and SET. The SET pin is a fairly
high impedance point and is susceptible to interference
from noisy signal lines such as the part’s CMOS outputs
OUT1 through OUT8.
7.Routetheoutputsignals,OUT1throughOUT8,awayfrom
the SET pin as soon as possible to minimize coupling.
8.WhenusingtheLTC6909withspreadspectrumdisabled,
an active output is connected to the MOD pin. This is
best done by routing the OUT1 signal under the part
as shown in Figure 6. The ground shield between this
traceandtheRSETresistorisveryimportanttominimize
coupling of the OUT1 signal into the SET pin.
ApplicAtions inForMAtion
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| LTC6909IMS#PBF | 功能描述:IC OSC SILICON 6.67MHZ 16-MSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 可編程計時器和振蕩器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 類型:振蕩器 - 晶體 計數(shù):- 頻率:- 電源電壓:2.3 V ~ 5.5 V 電流 - 電源:1.07mA 工作溫度:-30°C ~ 80°C 封裝/外殼:SOT-665 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:SS迷你型-5D 安裝類型:表面貼裝 其它名稱:AN8955SSMTXLTR |
| LTC6909IMS#TRPBF | 功能描述:IC OSC SILICON 6.67MHZ 16-MSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 可編程計時器和振蕩器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:45 系列:- 類型:溫度 - 補(bǔ)償晶體振蕩器（TCXO） 計數(shù):- 頻率:25MHz 電源電壓:3.135 V ~ 3.465 V 電流 - 電源:1.5mA 工作溫度:-40°C ~ 85°C 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 包裝:管件 供應(yīng)商設(shè)備封裝:16-SOIC W 安裝類型:表面貼裝 |
| LTC6909IMS-PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:1 to 8 Output, Multiphase Silicon Oscillator with Spread Spectrum Modulation |
| LTC6909IMS-TRPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:1 to 8 Output, Multiphase Silicon Oscillator with Spread Spectrum Modulation |
| LTC690C | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Microprocessor Supervisory Circuits |
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