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參數(shù)資料
| 型號： | LTC6908HS6-2#TRMPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OSC SILICON 10MHZ TSOT23-6 |
| 標準包裝： | 500 |
| 類型： | 振蕩器 - 硅 |
| 頻率： | 50kHz ~ 10MHz |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電流 - 電源： | 1.25mA |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | SOT-23-6 細型，TSOT-23-6 |
| 包裝： | 帶卷 (TR) |
| 供應商設備封裝： | TSOT-23-6 |
| 安裝類型： | 表面貼裝 |
LTC6908-1/LTC6908-2
11
690812fa
RSET ()
100
STARTUP
DELAY
(
s)
1000
1k
100k
1M
10M
690812 F07
10
10k
10000
TA = 25°C
V+ = 3V
and load response are maintained while peak electromag-
netic radiation (or conduction) is reduced. Output ripple
may be somewhat increased, but its behavior is very much
like noise and its system impact is benign.
HIGH FREQUENCY REJECTION
Using the LTC6908 in spread spectrum mode naturally
eliminates any concerns for output frequency accuracy
and stability as it is continually hopping to new settings.
In xed frequency applications however, some attention to
V+ supply voltage ripple is required to minimize additional
output frequency error. Ripple frequency components on
the supply line near the programmed output frequency of
the LTC6908 in excess of 30mVP-P could create an addi-
tional 0.2% of frequency error. In applications where a xed
frequency LTC6908 output clock is used to synchronize
the same switching regulator that provides the V+ supply
to the oscillator, noticeable jitter of the clock may occur
if the ripple exceeds 30mVP-P.
START-UP TIME
The start-up time and settling time to within 1% of the nal
value can be estimated by tSTART ≈ RSET (2.5s/k) + 10s.
For instance, with RSET = 100k, the LTC6908 will settle to
within 1% of its 1MHz nal value in approximately 260s.
APPLICATIO S I FOR ATIO
WU
U
Figure 7 shows start-up times for various RSET resistors.
An internal counter mutes the outputs for the rst 64 clock
cycles after power-up, ensuring that the rst clock cycle
is close to the desired operating frequency.
JITTER
The Peak-to-Peak Jitter vs Output Frequency graph, in
the Typical Performance Characteristics section, shows
the typical clock jitter as a function of oscillator frequency
and power supply voltage. These specications assume
that the capacitance on SET is limited to less than 10pF,
as suggested in the Pin Functions description. If this
requirement is not met, the jitter will increase.
Figure 7. Start-Up Time
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