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參數(shù)資料
| 型號(hào)： | LTC6902CMS#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OSC SILICON 20MHZ 10MSOP |
| 產(chǎn)品目錄繪圖： | LTC6902CMS#PBF Top |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 類型： | 振蕩器 - 硅 |
| 頻率： | 100kHz ~ 20MHz |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電流 - 電源： | 2.5mA |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 包裝： | 管件 |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 1715 (CN2011-ZH PDF) |
LTC6902
9
6902f
divider goes through further division. In addition to fur-
ther division, the duty cycle of the output depends on the
multiphase mode selected. Figure 4 shows the waveform
at each output for 2-, 3- and 4-phase modes.
2-Phase Mode
In 2-phase mode, all outputs are nominally 50% duty
cycle. OUT1 and OUT2 are 180 degrees out of phase.
Stated differently, OUT2 is OUT1 inverted. However, OUT2
THEORY OF OPERATIO
U
is not simply OUT1 routed through a standard logic
inverter. This would lead to substantial delay for OUT2’s
transitions from OUT1’s transitions. OUT1 and OUT2 are
created by a delay matched inverting circuit. Apart from
the basic inversion, the delay matching is determined by
analog circuit parameters. With this type of design, OUT1
and OUT2 transitions are typically within 100ps. OUT3 and
OUT4 are replications of OUT1 and OUT2 respectively.
Since the two phases are generated via delay matched
inverters, there is not any further division and the param-
eter M in the frequency setting equation is 1 (M = 1).
3-Phase Mode
In 3-phase mode, OUT1, OUT2 and OUT3 are active and all
three outputs have a 33.3% duty cycle. OUT4 is not active
and is at a logic low state. The three active outputs are all
120 degrees out of phase. OUT2 lags OUT1 by 120 degrees
and OUT3 lags OUT2 by 120 degrees. The signals are
generated by a shift register. The output frequency is the
programmable divider’s output further divided 3 (M = 3).
4-Phase Mode
In 4-phase mode, all outputs have a 50% duty cycle. The
outputs are all 90 degrees out of phase. OUT2 lags OUT1
Figure 3. RSET vs Desired Output Frequency
(PH = GND, 2-Phase, M = 1)
OUT1
2-PHASE, PH = GND
OUT2
OUT3
OUT4
OUT1
3-PHASE, PH = OPEN
OUT2
OUT3
OUT4
OUT1
4-PHASE, PH = V+
OUT2
OUT3
OUT4
M = 1
DUTY CYCLE = 50%
M = 3
DUTY CYCLE = 33%
(OUT4 = LOGIC LOW)
M = 4
DUTY CYCLE = 50%
69012 F04
Figure 4. Mulitphase Output Waveforms
DESIRED OUTPUT FREQUENCY (Hz)
10
R
SET
(k
)
100
1k
100k
1M
10M
69012 F03
1
10k
10000
1000
100M
÷100
÷10
÷1
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