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參數(shù)資料
| 型號： | LTC6900IS5#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OSC SILICON 20MHZ TSOT23-5 |
| 標準包裝： | 2,500 |
| 類型： | 振蕩器 - 硅 |
| 頻率： | 1kHz ~ 20MHz |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電流 - 電源： | 920µA |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | SOT-23-5 細型，TSOT-23-5 |
| 包裝： | 帶卷 (TR) |
| 供應商設(shè)備封裝： | TSOT-23-5 |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | LTC6900IS5TR |
LTC6900
5
6900fa
PIN FUNCTIONS
V+ (Pin 1): Voltage Supply (2.7V ≤ V+ ≤ 5.5V). This supply
must be kept free from noise and ripple. It should be by-
passed directly to a ground plane with a 0.1μF capacitor.
GND (Pin 2): Ground. Should be tied to a ground plane
for best performance.
SET (Pin 3): Frequency-Setting Resistor Input. The value
of the resistor connected between this pin and V+ deter-
mines the oscillator frequency. The voltage on this pin is
held by the LTC6900 to approximately 1.1V below the V+
voltage. For best performance, use a precision metal lm
resistor with a value between 10kΩ and 2MΩ and limit
the capacitance on this pin to less than 10pF.
DIV (Pin 4): Divider-Setting Input. This three-state input
selects among three divider settings, determining the value
of N in the frequency equation. Pin 4 should be tied to GND
for the ÷1 setting, the highest frequency range. Floating
Pin 4 divides the master oscillator by 10. Pin 4 should be
tied to V+ for the ÷100 setting, the lowest frequency range.
To detect a oating DIV pin, the LTC6900 attempts to pull
the pin toward midsupply. Therefore, driving the DIV pin
high requires sourcing approximately 2μA. Likewise, driv-
ing DIV low requires sinking 2μA. When Pin 4 is oated,
it should preferably be bypassed by a 1nF capacitor to
ground or it should be surrounded by a ground shield to
prevent excessive coupling from other PCB traces.
OUT (Pin 5): Oscillator Output. This pin can drive 5kΩ and/
or 10pF loads. Heavier loads may cause inaccuracies due
to supply bounce at high frequencies. Voltage transients,
coupled into Pin 5, above or below the LTC6900 power
supplies will not cause latchup if the current into/out of
the OUT pin is limited to 50mA.
BLOCK DIAGRAM
–
+
1
3
GAIN = 1
V+
VBIAS
IRES
RSET
SET
GND
PATENT PENDING
MASTER OSCILLATOR
PROGRAMMABLE
DIVIDER (N)
(÷1, 10 OR 100)
VRES = (V
+ – VSET) = 1.1V TYPICALLY
IRES
(V+ – VSET)
MO = 10MHz 20kΩ
THREE-STATE
INPUT DETECT
GND
V+
2μA
6900 BD
2μA
OUT
DIVIDER
SELECT
5
DIV
4
2
+
–
+
–
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