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參數(shù)資料
| 型號： | LTC6702ITS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 0K |
| 描述： | IC COMP LOW VOLT TSOT23-8 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 通用 |
| 元件數(shù)： | 2 |
| 輸出類型： | CMOS，推挽式，滿擺幅，TTL |
| 電壓 - 電源，單路/雙路(±)： | 1.7 V ~ 5.5 V |
| 電壓 - 輸入偏移（最小值）： | 3.5mV @ 3V |
| 電流 - 靜態(tài)（最大值）： | 32µA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 70dB CMRR，65dB PSRR |
| 傳輸延遲（最大）： | 450ns |
| 磁滯： | 5mV |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | SOT-23-8 薄型，TSOT-23-8 |
| 安裝類型： | 表面貼裝 |
| 包裝： | 帶卷 (TR) |
LTC6702
3
6702fa
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V+
Supply Voltage
Guaranteed by PSRR
l
1.7
5.5
V
I+
Supply Current per Comparator
V+ = 3V
l
24
30
40
μA
V+ = 5V
l
25
32
42
μA
VOS
Input Offset Voltage
(Note 5)
LTC6702C/LTC6702I
LTC6702H
l
1
3.5
5
6
mV
VHYST
Input Hysteresis Voltage
(Note 5)
LTC6702C/LTC6702I
LTC6702H
l
2.5
1.6
4.3
6.2
7.2
8.2
mV
ΔVOS/ΔT
Input Offset Voltage Drift
(Note 5)
l
6
μV/
°C
IIN
Input Leakage Current
LTC6702C/LTC6702I
LTC6702H
l
0.001
1
10
nA
CMRR
Common Mode Rejection Ratio
VCM = –0.1V to VDD – 1.2V
l
58
56
70
dB
Input Voltage Range
Guaranteed by CMRR
l
–0.1
VDD – 1.2
V
PSRR
Power Supply Rejection Ratio
V+ = 1.7V to 5.5V, VCM = 0.5V
l
56
54
65
dB
VOL
Output Swing Low
Overdrive = 20mV (Note 6)
ISINK = 100μA
ISINK = 15mA
l
10
250
mV
VOH
Output Swing High
Overdrive = 20mV (Note 6)
ISOURCE = 100μA
ISOURCE = 15mA
l
10
350
mV
tPD
Propagation Delay
(Note 7)
l
320
450
500
ns
ΔtPD
Differential Propagation Delay
Between Channels
4
ns
tSKEW
Propagation Delay Skew
Between tPDLH/tPDHL
4
ns
tr
Output Rise Time
11
ns
tf
Output Fall Time
15
ns
fMAX
Maximum Toggle Frequency
3.2
MHz
ISC
Short-Circuit Current
V + = 5V
±250
mA
The l denotes the specications which apply over the full specied
temperature range, otherwise specications are at TA = 25°C. V+ = 3V, VCM = 1.5V, COUT = 20pF, unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: A heat sink may be required to keep the junction temperature
below absolute maximum. This depends on the power supply voltage and
how many comparators are shorted. The
θJA specied for the DC and
TS packages is with minimal PCB heat spreading metal. Using expanded
metal area on all layers of a board reduces this value.
Note 3: The LTC6702C and LTC6702I are guaranteed functional over
the temperature range of –40°C to 85°C. The LTC6702H is guaranteed
functional over the operating temperature range of –40°C to 125°C.
Note 4: The LTC6702C is guaranteed to meet specied performance from
0°C to 70°C. The LTC6702C is designed, characterized and expected to
meet specied performance from –40°C to 85°C but is not tested or
QA sampled at these temperatures. The LTC6702I is guaranteed to meet
specied performance from –40°C to 85°C. The LTC6702H is guaranteed
to meet specied performance from –40°C to 125°C.
Note 5: The LTC6702 comparators include internal hysteresis. The offset
voltage is dened as the average of the input voltages (trip points)
required to change the output in each direction minus VCM, while the
hysteresis voltage is the difference of these trip points.
Note 6: Output voltage swings are measured between the output and
power supply rails.
Note 7: Propagation delay is for 200mV steps, and 50mV of overdrive.
Overdrive is measured relative to the positive and negative trip points.
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