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參數(shù)資料
| 型號： | LTC5564IUD#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQCC16 |
| 封裝： | 3 X 3 MM, LEAD FREE, PLASTIC, MO-220WEED-2, QFN-16 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大小： | 146K |
| 代理商： | LTC5564IUD#TRPBF |
LTC5564
9
5564f
Propagation Delay, Slew Rate and Response Time
The LTC5564 has been designed for high slew rate op-
eration. For RF input power levels of 10dBm to 16dBm
and a GAIN1 setting, the internal amplifier will slew at
350V/μs. In a given gain setting slew rate will be maximized
for larger input power levels. Slew rate will degrade with
smaller RFIN amplitude signals or when the amplifier gain
is increased. See Electrical Characteristics.
The LTC5564 has been designed to function as a positive
peak detector. Consequently, the device responds to a
rising signal at the RF detector input much more rapidly
than a falling signal. Correspondingly, the rising edge of
VOUT transitions much more rapidly than the falling edge
transitions as shown in Figure 3.
When operating in unity gain with a 10dBm to 16dBm RF
input signal, the propagation delay to fifty percent ΔVOUT
is approximately 7.0ns.
The operational amplifier has been internally compensated
to provide 75MHz bandwidth with VOUT = 500mV and a
GAIN1 mode setting. With no RF input the output offset
will be approximately 290mV. Lowering the output offset
will degrade bandwidth performance. See the Typical
Performance Characteristics.
APPLICATIONS INFORMATION
Loading, Bypass Capacitors and Board Layout
The LTC5564 has been designed to directly drive a capaci-
tive load of 10pF at VOUT. When driving a capacitive load
greater than 10pF a series resistance should be added
between VOUT and the load to maintain good stability. This
resistance should be placed as close to VOUT as possible.
See Table 2 for typical series resistor values for various
capacitive loads.
Table 2. Typical Series Resistor Values for VOUT
Capacitive Loading
CLOAD
R SERIES
Up to 10pF
0Ω
11pF to 20pF
40Ω
21pF to 100pF
68Ω
Greater Than 100pF
100Ω
Good layout practice and proper use of bypass capacitors
will improve circuit performance and reduce the possibility
of measurement error. Bypass capacitors should be used
for pins VCCRF, VCCA, VCCP, VOUTADJ and VREF. Bypass
capacitors should be connected as close to the LTC5564
as possible. All ground return path lengths and ohmic
losses should be minimized. See Figure 5 in the Applica-
tions Information section for the demo board schematic
showing these bypass capacitances.
The LTC5564 return path for all supply currents is through
the Pin 17 exposed pad. A high resistance path from the
Pin 17 exposed pad to power supply ground will cause
a VOUT output offset error. Board layout and connections
that minimize ohmic losses from the Pin 17 exposed pad
to power supply ground will reduce this error. Measure-
ments being made relative to LTC5564 ground should be
made as close to the Pin 17 exposed pad to reduce errors.
Figure 3. VOUT Pulse Response, PIN = 8dBm
10ns/DIV
5564 F03
VOUT
500mV/DIV
ASK MODULATED RF
INPUT SIGNAL START
VCC = 5V
ASK MODULATION FREQUENCY 2.7GHz
GAIN1
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