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參數(shù)資料
| 型號： | LTC4425EMSE#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO12 |
| 封裝： | LEAD FREE, PLASTIC, MSOP-12 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 239K |
| 代理商： | LTC4425EMSE#PBF |
LTC4425
10
4425f
OPERATION
Thermal Regulation
In either mode, if the die temperature starts to approach
105°C due to internal power dissipation, a thermal regula-
tor limits the die temperature to approximately 105°C by
reducing the charge current. Even in thermal regulation,
the PROG pin continues to give an indication of the charge
current. The thermal regulation protects the LTC4425 from
excessive temperature and allows the user to push the
limits of the power handling capability of a given circuit
board without the risk of damaging the LTC4425 or the
external components. Another benet of this feature is that
the charge current can be set according to typical, rather
than worst-case, ambient temperatures for a given applica-
tion with the assurance that the charger will automatically
reduce the charge current in worst-case conditions.
Voltage Clamp Circuitry
The LTC4425 is equipped with circuitry to limit the voltage
across any supercap of the stack to a maximum allowable
voltage VCLAMP. There are two preset voltages, 2.45V or
2.7V, for VCLAMP selectable by the SEL pin. The SEL pin
should be set to logic low for lower VCLAMP voltage of
2.45V and to logic high for the higher VCLAMP voltage of
2.7V. If the voltage across the bottom capacitor, i.e., the
VMID pin voltage reaches VCLAMP rst, an NMOS shunt
transistor turns on and starts to bleed charge off of the
bottom capacitor to GND. Similarly, if the voltage across
the top capacitor, VTOP, reaches the VCLAMP voltage rst, a
PMOS shunt transistor turns on and starts to bleed charge
off of the top capacitor to the bottom one.
When the voltage across any of the supercaps reaches
within 50mV of VCLAMP, a transconductance amplier
starts to cut back the charge current linearly. By the time
any of the shunt devices are on, the charge current gets
reduced to 1/10 of the programmed value and stays at
this reduced level as long as the shunt device is on. This
is to prevent the shunt devices from getting damaged by
excessive heat. The comparators that control the shunt
devices have a 50mV hysteresis meaning that when the
voltage across either capacitor is reduced by 50mV, the
shunt devices turn off and normal charging resumes with
full charge current unless limited by any of the other am-
pliers controlling the gate of the charger FET. In the event
both capacitors exceed their maximum allowable voltage,
VCLAMP, the main charger FET completely shuts off and
both shunt devices turn on. Both shunt devices are actually
current mirrors guaranteed to shunt more current away
than that coming through the charger FET.
Leakage Balancing Circuitry
The LTC4425 is equipped with an internal leakage balancing
amplier, LBA, which servos the midpoint, i.e., VMID pin
voltage, to exactly half of the output voltage, VOUT.However
it has a very limited source and sink capability of approxi-
mately 1mA. It is designed to handle slight mismatch of
the supercaps due to leakage currents; not to correct any
gross mismatch due to defects. The balancer is only active
as long as there is an input present. The internal balancer
eliminates the need for external balancing resistors.
Short-Circuit Current Limit
In the event the PROG pin gets shorted to GND, the LTC4425
limits the PROG pin current to approximately 3mA which,
in turn, limits the maximum charge current to about 3A.
While in short-circuit, if one of the supercaps approaches
within 50mV of its maximum allowable voltage, VCLAMP,
a current-limit foldback circuit cuts back the short-circuit
current limit to approximately 1/10 of its full value or to
about 300mA.
Supply Status Monitor
The LTC4425 includes an input power-fail comparator, PFC,
which monitors the input voltage VIN via the PFI pin. At any-
time, if VIN falls below a certain externally program-mable
threshold, it reports the undervoltage situation by pulling
down the open-drain output PFO low. This under-voltage
threshold is programmed by connecting an external resis-
tor divider network (consisting of RPF1 andRPF2) between
VIN and the PFI_RET pins. When the part is enabled, a low
RDS(ON) (approx. 13Ω) internal pull-down transistor pulls
the bottom end of RPF2, i.e., the PFI_RET pin to GND to
complete the divider network. When the part is disabled,
this transistor opens RPF2 from GND, thereby saving the
current drawn by the divider network. The power-fail com-
parator has a built-in lter to reject any transient supply
glitch that is less than 10μS long.
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