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參數(shù)資料
| 型號： | LTC4302IMS-1#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 298K |
| 描述： | IC BUFFER 2-WIRE BUS 10-MSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 熱交換開關(guān) |
| 應(yīng)用： | 通用型緩沖器/總線擴(kuò)展器 |
| 內(nèi)部開關(guān)： | 是 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
LTC4302-1/LTC4302-2
3
sn430212 430212fs
ELECTRICAL CHARACTERISTICS
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T
A
= 25?/SPAN>C.
V
CC
= 2.7V to 5.5V (LTC4302-1), V
CC
= V
CC2
= 2.7V to 5.5V (LTC4302-2) unless otherwise noted.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The I
CC
tests are performed with the backplane-to-card connection
circuitry activated.
Note 3: When the GPIOs are in open-drain output or input mode, the logic
high voltage can be provided by a pull-up supply voltage ranging from
2.2V to 5.5V, independent of the V
CC
voltage.
Note 4: I
PULLUP,AC
varies with temperature and V
CC
voltage as shown in
the Typical Performance Characteristics section.
Note 5: The connection circuitry always regulates its output to a higher
voltage than its input. The magnitude of this offset voltage as a function of
the pull-up resistor and V
CC
voltage is shown in the Typical Performance
Characteristics section.
Note 6: The specifications in this section illustrate the LTC4302-1/
LTC4302-2s compatibility with the I
2
C Fast Mode, the I
2
C Standard Mode
and SMBus specifications. See the Timing Diagram on page 5 for
illustrations of the timing parameters.
Note 7: C
B
= total capacitance of one bus line in pF.
Note 8: The digital interface circuit controls the data fall time only when
acknowledging or transmitting zeros during a read operation. The input-
output connection data and clock outputs meet the fall time specification
provided that the corresponding inputs meet the fall time specification.
Note 9: Guaranteed by design. Not subject to test.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
General Purpose I/Os
V
LOW
I/O Logic Low Voltage
I
SINK
= 10mA, V
CC
= 2.7V
q
0.36
0.8
V
V
HIGH
I/O Logic High Voltage
I
SOURCE
= 200礎(chǔ), V
CC
= 2.7V
q
2.4
V
I
LEAK
I/O Leakage Current
V
I/O
= 0V to 5.5V (Note 3)
q
?
礎(chǔ)
V
THRESH
Input Threshold Voltage
Input Mode
q
0.8
1.5
2.2
V
Rise Time Accelerators
I
PULLUP,AC
Transient Boosted Pull-Up Current
Positive Transition on SDA, SCL,
q
1
2
mA
Slew Rate = 0.8V/祍, V
CC
= 2.7V (Note 4)
Input-Output Connection
V
OS
Output-Input Offset Voltage
10k to V
CC
on SDA, SCL Pins (Note 5),
q
0
100
175
mV
C
IN
Digital Input Capacitance
(Note 9)
10
pF
V
OL
Output Low Voltage
SDA, SCL Pins, I
SINK
= 3mA
q
0
0.4
V
I
LEAK
Input Leakage Current
SDA, SCL Pins, V
CC
= 0V to 5.5V
q
?
礎(chǔ)
Connection Circuits Inactive
2-Wire Digital Interface Voltage Characteristics
V
LTH
Logic Threshold Voltage
q 0.3V
CC
0.5V
CC
0.7V
CC
V
I
LEAK
Digital Input Leakage
V
CC
= 0V to 5.5V
q
?
礎(chǔ)
V
OL
Digital Output Low Voltage
I
PULLUP
= 3mA Into SDAIN Pin
q
0.4
V
2-Wire Digital Interface Timing Characteristics (Note 6)
f
I2C,MAX
I
2
C Operating Frequency
(Note 9)
400
600
kHz
t
BUF
Bus Free Time Between Stop and Start
(Note 9)
0.75
1.3
祍
Condition
t
HD,STA
Hold Time After (Repeated) Start Condition (Note 9)
45
100
ns
t
SU,STA
Repeated Start Condition Setup Time
(Note 9)
30
0
ns
t
SU,STO
Stop Condition Setup Time
(Note 9)
30
0
ns
t
HD,DATI
Data Hold Time Input
(Note 9)
25
0
ns
t
HD,DATO
Data Hold Time Output
300
600
900
ns
t
SU,DAT
Data Setup Time
(Note 9)
50
100
ns
t
SP
Pulse Width of Spikes Suppressed by
(Note 9)
50
150
250
ns
the Input Filter
t
f
Data Fall Time
(Notes 7, 8, 9)
20 +
300
ns
0.1C
B
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