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參數(shù)資料
| 型號： | LTC4260IUH#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 18/30頁 |
| 文件大?。?/td> | 295K |
| 描述： | IC HOT SWAP CNTRL I2C 32-QFN |
| 標(biāo)準(zhǔn)包裝： | 73 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 8.5 V ~ 80 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN 裸露焊盤（5x5） |
| 包裝： | 管件 |
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LTC4260
18
4260fc
For more information www.linear.com/LTC4260
Digital Interface
The LTC4260 communicates with a bus master using
a 2-wire interface compatible with the I
2
C bus and the
SMBus, an I
2
C extension for low power devices.
The LTC4260 is a read-write slave device and supports
SMBus bus Read Byte, Write Byte, Read Word and Write
Word commands. The second word in a Read Word com-
mand will be identical to the first word. The second word
in a Write Word command is ignored. The data formats
for these commands are shown in Figures 6 to 10.
Using Optoisolators with SDA
The LTC4260 separates the SDA line into SDAI and SDAO.
If optoisolators are not used then tie SDAI and SDAO
together to construct a normal SDA line. When using
optoisolators connect the SDAI to the output of the incom-
ing opto and connect the SDAO to the input of the out-
going opto (see Figure 13).
START and STOP Conditions
When the bus is idle, both SCL and SDA must be high
(Figure 6). A bus master signals the beginning of a
transmission with a START condition by transitioning SDA
from high to low while SCL is high. When the master has
finished communicating with the slave, it issues a STOP
condition by transitioning SDA from low to high while SCL
is high. The bus is then free for another transmission.
I
2
C Device Addressing
Twenty-seven distinct bus address are configurable us-
ing the three-state ADR0-ADR2 pins. Table 1 shows the
correspondence between pin states and addresses. Note
that address bits B7 and B6 are internally configured to
10. In addition, the LTC4260 will respond to two special
addresses. Address (1011 111)b is a mass write used to
write to all LTC4260, regardless of their individual address
settings. The mass write can be masked by setting register
bit A4 to zero. Address (0001 100)b is the SMBus Alert
Response Address. If the LTC4260 is pulling low on the
ALERT pin, it will acknowledge this address using the
SMBus Alert Response Protocol.
applicaTions inForMaTion
Acknowledge
The acknowledge signal is used for handshaking between
the transmitter and the receiver to indicate that the last byte
of data was received. The transmitter always releases the
SDA line during the acknowledge clock pulse. When the
slave is the receiver, it must pull down the SDA line so that
it remains LOW during this pulse to acknowledge receipt
of the data. If the slave fails to acknowledge by leaving
SDA HIGH, then the master can abort the transmission by
generating a STOP condition. When the master is receiving
data from the slave, the master must pull down the SDA
line during the clock pulse to indicate receipt of the data.
After the last byte has been received the master will leave
the SDA line HIGH (not acknowledge) and issue a STOP
condition to terminate the transmission.
Write Protocol
The master begins communication with a START condition
followed by the seven bit slave address and the R/W bit set
to zero (Figure 7). The addressed LTC4260 acknowledges
this and then the master sends a command byte which
indicates which internal register the master wishes to write.
The LTC4260 acknowledges this and then latches the lower
three bits of the command byte into its internal Register
Address pointer. The master then delivers the data byte
and the LTC4260 acknowledges once more and latches the
data into its internal register. The transmission is ended
when the master sends a STOP condition. If the master
continues sending a second data byte, as in a Write Word
command, the second data byte will be acknowledged by
the LTC4260 but ignored (Figure 8).
Read Protocol
The master begins a read operation with a START condition
followed by the seven bit slave address and the R/W bit set
to zero (Figure 9). The addressed LTC4260 acknowledges
this and then the master sends a command byte that in-
dicates which internal register the master wishes to read.
The LTC4260 acknowledges this and then latches the lower
three bits of the command byte into its internal Register
Address pointer. The master then sends a repeated START
condition followed by the same seven bit address with the
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