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參數(shù)資料
| 型號(hào)： | LTC4259CGW |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 4-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO36 |
| 封裝： | 0.300 INCH, PLASTIC, SSOP-36 |
| 文件頁數(shù)： | 4/32頁 |
| 文件大小： | 324K |
| 代理商： | LTC4259CGW |
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LTC4259
12
4259i
Det/Class Restart PB (Address 18h): Detection/Classifi-
cation Restart Pushbutton Register, Write Only. Writing a
1 to any bit in this register will start or restart a single
detection or classification cycle at the corresponding port
in Manual mode. It can also be used to set the correspond-
ing bits in the Detect/Class Enable register (address 14h)
for ports in auto or semiauto mode. The lower 4 bits affect
detection on each port while the upper 4 bits affect
classification.
Power Enable PB (Address 19h): Power Enable Pushbutton
Register, Write Only. The lower four bits of this register set
the Power Enable bit in the corresponding Port Status
register; the upper four bits clear the corresponding Power
Enable bit. Setting or clearing the Power Enable bits via this
register will turn on or off the power in any mode except
shutdown, regardless of the state of detection or classifi-
cation. Note that tICUT, tSTART and disconnect events (if
enabled) will still turn off power if they occur.
The Power Enable bit cannot set if the port has turned off
due to a tICUT or tSTART fault and the tICUT timer has not yet
counted back to zero. See Applications Information for more
information on tICUT timing.
Clearing the Power Enable bits with this register also clears
the detect and fault event bits, the Port Status register, and
the Detection and Classification Enable bits for the affected
port(s).
Reset PB (Address 1Ah): Reset Pushbutton, Write Only.
Bit 4 returns the entire LTC4259 to the power-on reset state;
all ports are turned off, the AUTO pin is re-read, and all
registers are returned to their power-on defaults. Setting
bit 6 releases the Interrupt pin if it is asserted without af-
fecting the Event registers or the Interrupt register. When
the INT pin is released in this way, the condition causing
the LTC4259 to pull the INT pin down must be removed
before the LTC4259 will be able to pull INT down again. This
can be done by reading and clearing the event registers or
by writing a 1 into bit 7 of this register. Setting Bit 7 releases
the Interrupt pin, clears all the Event registers and clears
all the bits in the Interrupt register except bit 0 (Power Enable
Event). Bits 0-3 reset the corresponding port by clearing
the power enable bit, the detect and fault event bits, the
status register, and the detection and classification enable
bits for that port. Bit 5 is reserved; setting it has no effect.
Detect/Class Enable (Address 14h): Detection and Clas-
sification Enable, Read/Write. The lower four bits of this
register enable the detection circuitry at the correspond-
ing port if that port is in Auto or Semiauto mode. The upper
four bits enable the classification circuitry at the corre-
sponding port if that port is in Auto or Semiauto mode. In
manual mode, setting a bit in this register will cause the
LTC4259 to perform one classification or detection cycle
on the corresponding port. Writing to the Detect/Class
Restart PB (18h) has the same effect without disturbing the
Detect/Class Enable bits for other ports.
Timing Config (Address 16h): Global Timing Configura-
tion, Read/Write. Bits 0-1 program tDIS, the time duration
before an undercurrent condition is recognized as a viola-
tion of IMIN.Bits2-3programtICUT,thetimedurationbefore
an overcurrent condition is recognized as a tICUT fault. Bits
4-5 program tSTART, the time duration before an overcur-
rent condition at start-up is considered a tSTART fault. Note
that using tICUT and tSTART times other than the default is
not compliant with IEEE 802.3af and may double or qua-
druple the energy dissipated by the external MOSFETs
during fault conditions. Bits 6-7 are reserved and should
be read/written as 0. See Electrical Characteristics for timer
bit encoding.
Misc Config (Address 17h): Miscellaneous Configuration,
Read/Write. Bit 5 is the OSC Fail Mask; it is set by default.
When the OSC Fail Mask bit is clear, it prevents a failure on
the OSCIN pin from setting the OSC Fail bit and causing a
Supply Event Interrupt. Setting bit 7 enables the INT pin.
If this bit is reset, the LTC4259 will not pull down the INT
pin in any condition nor will it respond to the Alert Response
Address. This bit is set by default.
Pushbutton Registers
Note Regarding Pushbutton Registers: “Pushbutton” reg-
isters are specialized registers that trigger an event when
a 1 is written to a bit; writing a 0 to a bit will do nothing. Unlike
a standard read/write register, where setting a single bit
involves reading the register to determine its status, set-
ting the appropriate bit in software and writing back the
entire register, a pushbutton register allows a single bit to
be written without knowing or affecting the status of the
other bits in the register. Pushbutton registers are write-
only and will return 00h if read.
REGISTER FU CTIO S
U
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