參數(shù)資料
型號(hào): LTC4244CGN-1#TRPBF
廠商: Linear Technology
文件頁(yè)數(shù): 7/28頁(yè)
文件大?。?/td> 337K
描述: IC CTRLR HOTSWAP PCI 20-SSOP
標(biāo)準(zhǔn)包裝: 2,500
類型: 熱交換控制器
應(yīng)用: CompactPCI?
內(nèi)部開關(guān): 無(wú)
電源電壓: 3.3V,5V,±12V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 20-SSOP
包裝: 帶卷 (TR)
7
LTC4244/LTC4244-1
42441f
U
PI FU CTIO S
12V
IN
 (Pin 1): 12V Supply Input. A 0.5& switch is con-
nected between 12V
IN
 and 12V
OUT
 with a foldback current
limit. An undervoltage lockout circuit prevents the switches
from turning on while the 12V
IN
 pin voltage is less than 9V.
12V
IN
 also provides power to the LTC4244s internal V
CC
node.
V
EEIN
 (Pin 2): 12V Supply Input. A 1& switch is con-
nected between V
EEIN
 and V
EEOUT
 with a foldback current
limit. An undervoltage lockout circuit prevents the switches
from turning on while the V
EEIN
 pin voltage is greater than
9.25V. The V
EEIN
 undervoltage lockout function is dis-
abled for the LTC4244-1.
5V
OUT
 (Pin 3): 5V Output Sense. The PWRGD pin will not
pull low until the 5V
OUT
 pin voltage exceeds 4.61V. A 200&
active pull-down discharges 5V
OUT
 to ground when the
power switches are turned off.
TIMER (Pin 4): Current Fault Inhibit Timing Input and
Auxiliary V
CC
. Connect a capacitor from TIMER to GND.
When the LTC4244 is turned on, a 21礎(chǔ) pull-up current
source is connected to TIMER. Current limit faults will be
ignored until the voltage at the TIMER pin rises to within
1.6V of 12V
IN
. After the TIMER pin has completed ramp-
ing up, the TIMER capacitor serves as an auxiliary charge
reservoir for V
CC
  in the event the 12V
IN
  pin voltage
momentarily drops below the undervoltage lockout thresh-
old voltage. When the LTC4244 is turned off (OFF/ON >
2V), the TIMER pin is pulled down to GND. After the TIMER
pin voltage drops to within 0.8V of GND, the TIMER latch
is reset and the part is ready for another power cycle.
OFF/ON
 
(Pin 5): Digital Input. Connect the CPCI BD_SEL#
signal to the OFF/ON pin. When the OFF/ON pin is pulled
low, the GATE pin is pulled high by a 67礎(chǔ) current source
and the internal 12V and 12V switches are turned on.
When the OFF/ON pin is pulled high, the GATE pin will be
pulled to ground by a 60礎(chǔ) current source and the 12V and
12V switches turn off.
FAULT (Pin 6): Open-Drain Digital I/O. FAULT is pulled low
when a current limit fault is detected. Current limit faults
are ignored until the voltage at the TIMER pin is within 1.6V
of 12V
IN
. Once the TIMER cycle is complete, FAULT will
pull low and the LTC4244 latches off in the event of an
overcurrent fault. The part will remain in the latched off
state until the OFF/ON pin is cycled high then low. Forcing
the FAULT pin low with an external pull-down will cause
the part to latch into the off state after a 25祍 deglitching
time.
PWRGD (Pin 7): Open-Drain Digital Power Good Output.
Connect the CPCI HEALTHY# signal to the PWRGD pin.
PWRGD remains low while V
12VOUT
e 11.1V, V
3.3VOUT
e
2.9V, V
5VOUT
e 4.61V, and V
EEOUT
 d 11.1V. When any of
the supplies falls below its power good threshold voltage,
PWRGD will go high after a 14祍 deglitching time.
GND (Pin 8): Device Ground.
RESETIN (Pin 9): Digital Input. Connect the CPCI PCI_RST#
signal to the RESETIN pin. Pulling the RESETIN pin low will
cause RESETOUT to pull low. RESETOUT will also pull low
when PWRGD is high.
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