參數(shù)資料
型號： LTC4230CGN#TRPBF
廠商： Linear Technology
文件頁數(shù)： 16/36頁
文件大?。?/td> 384K
描述： IC CONTRLLR HOT SWAP TRPL 20SSOP
標準包裝： 2,500
類型： 熱交換控制器
應用： 通用
內(nèi)部開關： 無
電源電壓： 1.7 V ~ 16.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 20-SSOP（0.154"，3.90mm 寬）
供應商設備封裝： 20-SSOP
包裝： 帶卷 (TR)
16
LTC4230
 4230f
a start-up check to make sure the supply voltage is above
its 2.3V UVLO threshold (see Time Point 1). If the input
supply voltage is valid, the gate of the external pass
transistor is pulled to ground by the internal 200礎 current
source connected at the GATEn pin. The TIMER pin is held
low by an internal N-channel pull-down transistor (see
M6, LTC4230 Block Diagram) and the FILTER pin voltage
is pulled to ground by an internal 10礎 current source.
Once V
CCn
 and ON (the ON pin is >1.314V) are valid, the
LTC4230 checks to make sure that GATEn is OFF (V
GATEn
< 0.25V) at Time Point 2. An internal timing circuit is
enabled and the TIMER pin voltage ramps up at the rate
described by Equation 1. At Time Point 3 (the timing period
programmed by C
TIMER
), the TIMER pin voltage equals
V
TMR
 (1.234V). Next, the TIMER pin voltage ramps down
to Time Point 4 where the LTC4230 performs two checks:
(1) FILTER pin voltage is low (V
FILTER
 < 1.19V) and (2)
FAULT pin voltage is high (V
FAULT
  > 1.284V). If both
conditions are met, the LTC4230 begins a second timing
(soft-start) cycle.
Second Timing (Soft-Start) Cycle
At the beginning of the second timing cycle (Time Point 5),
the LTC4230s FAST COMPn is armed and an internal
10礎 current source working with an internal charge
pump provides the gate drive to the external pass transis-
tor. An expression for the GATEn voltage slew rate is given
by Equation 3:
V
SlewRate
dV
dt
A
C
GATE
GATE
GATE
n
n
n
,
=
?/DIV>
10
(3)
where C
GATEn
 = Power MOSFET gate input capacitance
(C
ISS
) for Channel n.
For example, a Si4410DY (a 30V N-channel power MOSFET)
exhibits an approximate C
GATE
 of 3300pF at V
GS
 = 10V. The
LTC4230s GATEn voltage rate-of-change (slew rate) for
this example would be:
V
SlewRate
dV
dt
A
pF
V
ms
GATE
GATE
n
n
,
.
=
?/DIV>
=
10
3300
3 03
The inrush current being delivered to the load while the
GATEn is ramping is dependent on C
LOADn
 and C
GATEn
.
Equation 4 gives an expression for the inrush current
during the second timing cycle:
I
dV
dt
C
A
C
C
INRUSH
GATE
LOAD
LOAD
GATE
=
=   ?/DIV>
n
n
n
n
"
"
10
(4)
For example, if C
GATEn
 = 3300pF and C
LOADn
 = 2000礔, the
inrush current charging C
LOADn
 is:
I
A
F
F
A
INRUSH
=   ?/DIV>
?/DIV>
?/DIV>
=
10
2000
0 0033
6 06
"
.
.
(5)
At Time Point 7, the output voltage trips FBCOMPns
threshold, signaling an output voltage power good con-
dition. RESET 2 and RESET 3 pull high. At Time Point 8,
RESET 1 asserts high, SLOW COMP is armed and the
LTC4230 enters a fault monitor mode.
SOFT-START WITH CURRENT LIMITING
During the second timing cycle, the inrush current is
described by Equation 4. Note that there is a one-to-one
correspondence in the inrush current to C
LOADn
. If the
inrush current is large enough to cause a voltage drop
greater than 50mV across the sense resistor, an internal
servo loop controls the operation of the 10礎 current
source at the GATEn pin to regulate the load current to:
I
mV
R
LIMIT SOFTSTART
SENSE
(
)n
n
=
50
(6)
For example, the inrush current is limited to 5A when
R
SENSEn
 = 0.01&.
In this fashion, the inrush current is controlled and C
LOADn
is charged up slowly during the soft-start cycle.
The timing diagram in Figure 6 illustrates the operation of
the LTC4230 in a normal power-up sequence with limited
inrush current as described by Equation 6. At Time Point 5,
the GATE pin voltage begins to ramp indicating that the
power MOSFET is beginning to charge C
LOADn
. At Time
Point 5, the inrush current causes a 50mV voltage drop
across R
SENSEn
 and an internal servo loop engages, limit-
ing the inrush current to a fixed level. At Time Point 6, the
GATEn pin voltage continues to ramp as C
LOADn
 charges
until V
OUTn
 reaches its final value. The charging current
APPLICATIO  S I FOR  ATIO
U
U
U
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