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參數(shù)資料
| 型號(hào)： | LTC4224IDDB-2#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 220K |
| 描述： | IC CNTRLR HOT SWAP DUAL 10-DFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 1 V ~ 6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 10-DFN-EP（3x2） |
| 包裝： | 帶卷 (TR) |
LTC4224-1/LTC4224-2
10
422412fa
APPLICATIONS INFORMATION
If there is signi cant supply lead inductance, a severe
output short may collapse the input to ground before the
LTC4224 can bring the current under control. In this case,
the undervoltage lockout activates after an 8約 lter delay,
and the GATE is pulled down by 1.5mA.
Resetting Faults
Following an overcurrent fault, the LTC4224-1 latches
off while the LTC4224-2 automatically restarts after a
four second cool down period. An overcurrent fault on
either supply causes the ECB for that supply to turn off
the MOSFET and pull the FAULT pin low. Faults are reset
by pulling the ON pin high for at least 20約, after which
the FAULT pin releases and the turn-on sequence begins.
Taking the lower supply below V
CCLO(UVL)
clears only that
supplys fault and the turn-on sequence commences im-
mediately. Pulling the higher supply below V
CC(UVL)
clears
both supplies faults and the turn-on sequence begins after
a 160ms UV turn-on delay. When both supplies are above
2.5V , either supply going low only resets its own fault.
For the auto-retry version (LTC4224-2), if the fault is not
cleared within four seconds, the latched fault will be cleared
automatically. FAULT will go high and the turn-on sequence
will begin. A persistent fault results in an auto-retry duty
cycle of about 0.1%. Figure 9 shows an auto-retry sequence
as a result of an overcurrent fault.
Gate Pin Voltage
The gate drive is compatible with logic level MOSFETs, but
caution is required if one supply is low. The guaranteed
range of gate drive is 4.5V to 7V , with a typical value of
5.5V . Each GATE pin is clamped with respect to V
CC
, the
higher of the two input supplies. When V
CC
is at 5V , both
GATE pins can be as high as 12V above ground. If the
lower supply is at 0V , the gate-to-source voltage of its
MOSFET can be 12V . In such applications, MOSFETs with
gate-to-source breakdown ratings of 12V or greater are
recommended.
Active Current Loop Compensation
The active current loop is compensated by the parasitic
capacitance of the external MOSFET . No further compensa-
tion components are normally required. In the case where a
MOSFET with less than 600pF of gate capacitance is chosen,
a 600pF compensation capacitor connected between the
GATE pin and ground may be required.
Supply Transient Protection
In applications where the supply inputs are fed directly
from the regulated output of the backplane supply, bulk
bypassing assures a spike-free operating environment.
In other applications where bulk bypassing is located far
from the LTC4224, spikes generated during output short-
circuit events could exceed the absolute maximum ratings
for V
CC
. To minimize such spikes, use wider traces or
heavier trace plating to reduce the power trace inductance.
Figure 10. Input Supply Transient Protection
Network for Applications without Input Capacitance
422412 F10
LTC4224
V
CC2
GND
SENSE2 GATE2
R2
0.010?/DIV>
V
CC2
V
OUT
C
LOAD2
Q2
FDS6911
+
R
SNUB
10?/DIV>
C
SNUB
0.1糉
Z1
SMAJ5.0A
Figure 9. Auto-Retry After Overcurrent Fault
1s/DIV
I
OUT
1A/DIV
GATE
2V/DIV
FAULT
5V/DIV
422412 F09
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