參數(shù)資料
型號： LTC4223CDHD-2#PBF
廠商： Linear Technology
文件頁數(shù)： 12/24頁
文件大?。?/td> 290K
描述： IC CNTRLR HOT SWAP DUAL 16-DFN
標準包裝： 73
類型： 熱交換控制器
應用： ATCA，MicroTCA?
內(nèi)部開關(guān)： 無
電源電壓： 2.7 V ~ 6 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 16-WFDFN 裸露焊盤
供應商設備封裝： 16-DFN（5x4）
包裝： 管件
LTC4223-1/LTC4223-2
12
422312f
APPLICATIONS INFORMATION
Turn-Off Sequence
The switches can be turned off by various conditions and
this is summarized in Table 1.
When the 12ON pin goes low, the external switch is turned
off with the GATE pin pulled to ground by 1mA current
sink. The
?/DIV>
1
?/DIV>
2
?/DIV>
P
?/DIV>
G
?/DIV>
O
?/DIV>
O
?/DIV>
D pin pulls high indicating that power is
no longer good, while an internal N-channel transistor dis-
charges the output to ground. Similarly, when the AUXON
pin goes low, the internal switch is turned off,
?/DIV>
A
?/DIV>
U
?/DIV>
X
?/DIV>
P
?/DIV>
G
?/DIV>
O
?/DIV>
O
?/DIV>
D
pulls high while its output is discharged to ground through
an internal N-channel transistor. Figure 3 shows the two
supplies being turned off by
?/DIV>
E
?/DIV>
N going high.
Card Presence Detect
In an AMC system,
?/DIV>
P
?/DIV>
S
?/DIV>
1 and
?/DIV>
P
?/DIV>
S
?/DIV>
0 signals are used to
detect the presence of a card upon insertion or removal.
Normally
?/DIV>
P
?/DIV>
S
?/DIV>
1 is connected to the
?/DIV>
E
?/DIV>
N pin with a pull-up
resistor. If AUXON or 12ON is high when the
?/DIV>
E
?/DIV>
N pin goes
low, indicating a board insertion, a timing cycle for contact
debouncing is initiated. Upon insertion, any bounces on the
?/DIV>
E
?/DIV>
N pin will re-start the timing cycle. When TIMER  nally
reaches its threshold during ramp up, the fault latches
will be cleared. If the
?/DIV>
E
?/DIV>
N pin remains low at the end of the
timing cycle, the switches are allowed to turn on.
If the
?/DIV>
E
?/DIV>
N pin is toggled from low to high, indicating board
removal, all the switches will be turned off after a 20約 delay.
Any latched faults will not be cleared. However, removing
the card could cause the
?/DIV>
E
?/DIV>
N pin voltage to bounce, clearing
the fault latches undesirably. This is prevented by blanking
the bounces internally with a TIMER ramp up period given
by C
T
 " 123[ms/糉] as shown in Figure 4.
Timer Functions
An external capacitor C
T
 connected from the TIMER pin
to ground is used to perform several functions.
1. Ignore contact debouncing during card insertion when
the device is enabled. The debounce cycle is given
by ramping up C
T
 with 10糀 current to TIMER high
threshold (1.235V) and then ramping down with 2糀
current to below TIMER low threshold (0.2V). This gives
an average debounce cycle time of C
T
 " 741[ms/糉].
After that, if any ON pin is pulled high and
?/DIV>
E
?/DIV>
N pin is
low, the switches can be turned on.
2. Blanking contact bounce on the
?/DIV>
E
?/DIV>
N pin that might
trigger unwanted fault clearing during card removal.
The blanking time is given by C
T
 " 123[ms/糉].
3. Fault  ltering during auxiliary supply power-up in analog
current limit. TIMER pulls up with 10糀 and pulls down
with 2糀. The  lter time is given by C
T
 " 123[ms/糉].
4. 12V supply fault  ltering during and after power-up
in analog current limit. TIMER pulls up with 200糀
and pulls down with 2糀. The  lter time is given by
C
T
 " 6[ms/糉].
5. For cooling off during an auto-retry cycle after
an overcurrent fault on auxiliary or 12V supply
(LTC4223-2). The cool-off time is given by C
T
 " 1482
[ms/糉] after an auxiliary supply fault and C
T
 " 1358[ms/
糉] after a 12V supply fault.
Figure 3. Normal Power-Down Sequence
Figure 4. Debouncing by TIMER during Card Removal
100ms/DIV
12PGOOD
5V/DIV
EN
5V/DIV
AUXOUT
5V/DIV
12V
OUT
5V/DIV
AUXPGOOD
5V/DIV
422312 F03
5ms/DIV
FAULT
2V/DIV
EN
2V/DIV
TIMER
1V/DIV
422312 F04
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