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參數(shù)資料
| 型號： | LTC4215IUFD-3#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24 |
| 封裝： | 4 X 5 MM, LEAD FREE, PLASTIC, MO-220, QFN-24 |
| 文件頁數(shù)： | 5/28頁 |
| 文件大小： | 307K |
| 代理商： | LTC4215IUFD-3#PBF |
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LTC4215-1/LTC4215-3
13
421513fc
The MOSFET is turned on by charging up the GATE with
a 20μA current source. When the GATE voltage reaches
the MOSFET threshold voltage, the MOSFET begins to
turn on and the SOURCE voltage then follows the GATE
voltage as it increases.
When the MOSFET is turning on, it ramps inrush current
up linearly at a dI/dt rate selected by capacitor CSS. Once
the inrush current reaches the limit set by the FB pin, the
dI/dt ramp stops and the inrush current follows the fold-
back prole as shown in Figure 2. The TIMER capacitor
integrates at 100μA during start-up and once it reaches its
threshold of 1.235V, the part checks to see if it is in current
limit, which indicates that it has started up into a short-
circuit condition. If this is the case, the overcurrent fault
bit, D2 in Table 5, is set and the part turns off. If the part
is not in current limit, the 25mV circuit breaker is armed
and the current limit is switched to 75mV. Alternately an
internal 100ms start-up timer may be selected by tying
the TIMER pin to INTVCC.
As the SOURCE voltage rises, the FB pin follows as set by
R7 and R8. Once FB crosses its 1.235V threshold, and the
start-up timer has expired, the GPIO1 pin, if congured
to indicate power-good, ceases to pull low and indicates
that power is now good. Alternately bit C3 can be read
to check power-good status, where a zero indicates that
power is good.
Figure 2. Power-Up Waveforms
If R6 and C1 are employed for a constant current during
start-up, which produces a constant dV/dt at the output,
a 20μA pull-up current from the gate pin slews the gate
upwards and the part is not in current limit. The start-up
TIMER may expire in this condition and an overcurrent
(OC) fault is not generated even though start-up has not
completed. Either the sense voltage increases to the
25mV CB threshold and generates an OC fault, or the FB
pin voltage crosses its 1.235V power good threshold and
is indicated in bit C3 as well as the GPIO1 pin if GPIO1 is
congured to do so.
GATE Pin Voltage
A curve of GATE-to-SOURCE drive vs VDD is shown in the
Typical Performance Characteristics. At minimum input
supply voltage of 2.9V, the minimum GATE-to-SOURCE
drive voltage is 4.7V. The GATE-to-SOURCE voltage is
clamped below 6.5V to protect the gates of logic level
N-channel MOSFETs.
Turn-Off Sequence
The GATE is turned off by a variety of conditions. A normal
turn-off is initiated by the ON pin going low or a serial bus
turn-off command. Additionally, several fault conditions
turn off the GATE. These include an input overvoltage
APPLICATIONS INFORMATION
VDD + 6V
VGATE
VOUT
GPIO1
(POWER GOOD)
ILOAD RSENSE
VDD
VSENSE
25mV
10mV
SS
LIMITED
FB
LIMITED
4215 F02
TIMER
EXPIRES
tSTARTUP
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